ISL6326BIRZ Intersil, ISL6326BIRZ Datasheet - Page 26

• Manufacturer Part Number: ISL6326BIRZ
• Description: IC CTRLR PWM 4PHASE BUCK 40-QFN
• Manufacturer: Intersil

Specifications of ISL6326BIRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 275kHz
• Duty Cycle: 25%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 275kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Based on the desired loadline R
resistor can be calculated by the following equation:
where N is the active channel number, R
resistor connected to the ISEN+ pin, and R
resistance of the current sense element, either the DCR of
the inductor or R
If one or more of the current sense resistors are adjusted for
thermal balance, as in Equation 31, the load-line regulation
resistor should be selected based on the average value of
the current sensing resistors, as given in the following
equation:
where R
the n
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.
COMPENSATING LOAD-LINE REGULATED
CONVERTER
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
The final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
poles and the ESR zero of the voltage-mode approximation
yields a solution that is always stable with very close to ideal
transient performance.
R
R
FB
FB
th
=
=
ISEN+ pin.
N R
--------------------------------- -
R
----------
R
ISEN(n)
LL
X
ISEN
R
∑
n
X
R
R
ISEN n ( )
is the current sensing resistor connected to
LL
SENSE
depending on the sensing method.
26
C
LL
and C
, the loadline regulation
C
.
ISEN
X
is the
is the sense
(EQ. 33)
(EQ. 34)
ISL6326B
The feedback resistor, R
outlined in Load-Line Regulation Resistor. Select a target
bandwidth for the compensated system, f
bandwidth must be large enough to assure adequate
transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f
to the L-C pole frequency and the ESR zero frequency. For
each of the three cases which follow, there is a separate set
of equations for the compensation components.
In Equation 35, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
Case 1:
Case 2:
Case 3:
FIGURE 16. COMPENSATION CONFIGURATION FOR
R
FB
LOAD-LINE REGULATED ISL6326B CIRCUIT
R
C
-------------------
2π LC
f
R
C
-------------------
2π LC
R
C
V
0
+
-
DROOP
C
C
C
C
C
C
R
>
1
1
C
=
=
=
=
----------------------------- -
2πC ESR
=
=
C
R
------------------------------------------------------------ -
(
R
0.75V
------------------------------------------------ -
R
----------------------------------- -
2πV
FB
2π
2
2πV
≤
>
FB
FB
FB
(
C
(OPTIONAL)
1
0.75V
f
, has already been chosen as
f
C
)
0
0
V
--------------------------------------------
2
PP
2πf
----------------------------------- -
----------------------------------------- -
0.75 V
PP
<
PP
IN
f
0
----------------------------- -
2πC ESR
0.75V
0.75V
R
2
2π f
0
)
R
0.75 V
(
(
IN
FB
V
ESR
V
2π
FB
PP
COMP
VDIFF
pp
0
IN
(
f
1
0
)
V
f
IN
IN
2
0
R
FB
(
pp
) C
IN
ESR
LC
f
FB
0
L
2
L
)
LC
0
LC
)
. The target
April 21, 2006
(EQ. 35)
FN9286.0
0