ISL6336BIRZ Intersil, ISL6336BIRZ Datasheet - Page 13

• Manufacturer Part Number: ISL6336BIRZ
• Description: IC CTRLR PWM SYNC BUCK 48-QFN
• Manufacturer: Intersil

Specifications of ISL6336BIRZ

• Applications: Controller, Intel VR11.1
• Voltage - Input: 3 ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.5 ~ 1.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Non-CI or (N - 1) - CI Drops to 1-Phase
Non-CI or (N - 2) - CI Drops to 2-Phase
2-Phase CI Drops to 1-Phase
2-Phase CI Drops to 2-Phase
Normal PWM CCM Mode
frequency set by the resistor between the FS pin and
ground. The PWM signals command the MOSFET drivers to
turn on/off the channel MOSFETs.
In the default 6-phase operation, the PWM2 pulse happens
1/6 of a cycle after PWM1, the PWM3 pulse happens 1/6 of
a cycle after PWM2, etc.
The ISL6336B works in a 1- to 6-phase configuration.
Connecting the PWM6 pin to VCC selects 5-phase operation
and the pulse times are spaced in 1/5 cycle increments.
Connecting the PWM5 pin to VCC selects 4-phase operation
and the pulse times are spaced in 1/4 cycle increments, etc.
When PSI# is pulled LOW, indicating low power operation of
the processor, the controller reduces the number of active
phases and operates 1- or 2-phases to improve efficiency
based on the logic in Table 2. Table 1 shows which phases
will be active when PSI# = 0 based on the phase count of the
application. For example, If operating in a 6-phase
configuration, phase 1 will be active if dropping to 1-phase
and phases 1 and 4 will be active if dropping to 2-phases.
6-Phase
5-Phase
4-Phase
3-Phase
2-Phase
1-Phase
The SS and FS pins are used to program the controllers PWM
behavior in configurations using standard inductors, 2-phase
coupled inductors or (N - 1)/(N - 2)-phase coupled inductors
when PSI# goes LOW. Two-phase coupled inductors refer to
inductor structures that magnetically couple 2-phases together.
(N - 1) and (N - 2) coupled inductors refer to structures that
couple all phases together except for the 1- or 2-phases that
remain active in PSI# mode. N refers to the programmed
number of active phases in normal operation, PSI# = 1 (See
Table 1). Each case yields different PWM output behavior on
PHASE
COUNT
TABLE 1. NUMBER OF ACTIVE PHASES AND PWM FIRING
CONFIGURATION
1 - 2 - 3 - 4 - 5 - 6
TABLE 2. PHASE DROPPING BEHAVIOR
1 - 2 - 3 - 4 - 5
SEQUENCE
OPERATION
SEQUENCE
1 - 2 - 3- 4
NORMAL
PHASE
1 - 2 - 3
1 - 2
1
13
PWM5:6 = VCC
PWM4:6 = VCC
PWM3:6 = VCC
PWM2:6 = VCC
PWM6 = VCC
PWM/VCC
PSI#
0
0
0
0
1
-
RESISTOR
GND
GND
VCC
VCC
FS
x
Phase 1/4
Phase 1/3
Phase 1/3
Phase 1/2
Phase 1/2
PHASES
PSI# = 0
RESISTOR
ACTIVE
GND
GND
VCC
VCC
-
SS
x
ISL6336B
both the dropped phase(s) and active phases as PSI# is
asserted and de-asserted. In Table 2, ‘VCC’ means that the
resistor is connected from the respective pin to VCC and ‘GND’
means the resistor is connected from the respective pin to
GND.
When PSI# goes LOW, the dropped phase’s PWM signal is
forced LOW for a minimum time, 200ns typically, and then is
driven to 1/2*VCC while the remaining active phase PWM(s)
sends out a repetitive 3-level PWM pattern that the
dedicated VR11.1 drivers (ISL6622/ISL6620) can decode
and then enter diode emulation mode.
During soft-start or overcurrent hiccup mode all phases will be
operating despite the state of the PSI# pin. Once VR_RDY is
asserted the state of the PSI# pin is considered. In addition, a
LOW signal at the H_CPURST_N pin disables PSI# mode.
The state of the PSI# signal will not be recognized as LOW
until approximately 45ms (see “Electrical Specifications” table
on page 7 for the delay time range) after H_CPURST_N
returns to a logic HIGH state. The LOW and HIGH thresholds
are 0.4V and 0.8V respectively. A logic LOW can be obtained
by pulling this pin to ground with a suitable small signal
device, while a logic HIGH can be obtained by leaving the pin
open or connecting to the processor VTT (~1.1V) via a
suitable pull-up. If the PSI# lockout is not desired at any time
during the operation of the IC, then connect H_CPURST_N to
VCC.
This unique function eliminates the required external
circuitry for proper PSI# operation of Intel’s Eaglelake
chipset platforms, reducing cost and PCB space. This
function can be disabled making the ISL6336B compatible
with the ISL6336 for other platform implementations.
A high PSI# input signal will force the controller back into
CCM normal operation and all phases will be activated to
sustain a heavy load transient and to increase efficiency at
higher loads.
While the controller is operational (VCC above POR,
EN_VTT and EN_PWR are both high, valid VID inputs), it
can pull the PWM pins to ~40% of VCC (~2V for 5V VCC
bias) during various stages, such as soft-start delay, phase
shedding operation, or fault conditions (OC or OV events).
The matching driver's internal PWM resistor divider can
further raise the PWM potential, but not lower it below the
level set by the controller IC. Therefore, the controller's
PWM outputs are directly compatible with Intersil drivers that
require 5V PWM signal amplitudes. Drivers requiring 3.3V
PWM signal amplitudes are generally incompatible.
Switching Frequency
The switching frequency is determined by the selection of
the frequency-setting resistor, R
FS pin to GND or VCC (see “Typical Application - 5-Phase
Buck Converter with Thermal Compensation” on page 5 and
“Typical Application - 4-Phase Buck Converter with Coupled
T
, which is connected from
August 31, 2010
FN6696.2