ISL6336BIRZ Intersil, ISL6336BIRZ Datasheet - Page 15

• Manufacturer Part Number: ISL6336BIRZ
• Description: IC CTRLR PWM SYNC BUCK 48-QFN
• Manufacturer: Intersil

Specifications of ISL6336BIRZ

• Applications: Controller, Intel VR11.1
• Voltage - Input: 3 ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.5 ~ 1.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

efficiency due to the additional power loss on the current
sense element R
The same capacitor C
between ISEN- and ISEN+ signals. Select the proper C
keep the time constant of R
to 27ns.
Equation 7 shows the ratio of the channel current to the
sensed current I
The inductor DCR value will increase as the temperature
increases. Therefore the sensed current will increase as the
temperature of the current sense element increases. In order
to compensate the temperature effect on the sensed current
signal, a Positive Temperature Coefficient (PTC) resistor can
be selected for the sense resistor R
temperature compensation function of ISL6336B should be
utilized instead. The integrated temperature compensation
function is described in “External Temperature
Compensation” on page 24.
Channel-Current Balance
The sensed current I
together and divided by the number of active channels. The
resulting average current I
total load current. Channel-current balance is achieved by
comparing the sensed current of each channel to the
average current to make an appropriate adjustment to the
PWM duty cycle of each channel with Intersil’s patented
current-balance method.
Channel-current balance is essential in achieving the
thermal advantage of multiphase operation. With good
current balance, the power loss is equally dissipated over
multiple devices and a greater area.
Voltage Regulation
The compensation network shown in Figure 6 assures that
the steady-state error in the output voltage is limited only to
I
SEN
FIGURE 5. SENSE RESISTOR IN SERIES WITH INDUCTORS
ISL6336B
INTERNAL CIRCUIT
=
I
L
CURRENT
⋅
SENSE
I
R
-----------------------
SEN
R
SENSE
I
ISEN
n
=
SEN
SENSE
I
L
R
------------------------- -
.
n
R
SENSE
from each active channel are summed
T
ISEN
.
is needed to match the time delay
+
-
AVG
ISEN
15
provides a measure of the
ISEN-(n)
ISEN+(n)
L
and C
ISEN
T
R
I
SENSE
L
, or the integrated
(R
ISEN
R
C
ISEN(n)
T
C
V
OUT
x C
OUT
T
) close
(EQ. 7)
T
to
ISL6336B
the error in the reference voltage (output of the DAC) and
offset errors in the OFS current source, remote-sense and
error amplifiers. Intersil specifies the guaranteed tolerance of
the ISL6336B to include the combined tolerances of each of
these elements.
The output of the error amplifier, V
sawtooth waveforms to generate the PWM signals. The
PWM signals control the timing of the Intersil MOSFET
drivers and regulate the converter output to the specified
reference voltage. The internal and external circuitries which
control the voltage regulation are illustrated in Figure 6.
The ISL6336B incorporates an internal differential remote-
sense amplifier in the feedback path. The amplifier removes
the voltage error encountered when measuring the output
voltage relative to the local controller ground reference point
resulting in a more accurate means of sensing output
voltage. Connect the microprocessor sense pins to the
non-inverting input, VSEN, and inverting input, RGND, of the
remote-sense amplifier. The remote-sense output, V
connected to the inverting input of the error amplifier through
an external resistor.
A digital-to-analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID7
through VID0. The DAC decodes the 8-bit logic signal (VID)
into one of the discrete voltages shown in Table 3. Each VID
input has an internal 30µA minimum pull-up to VCC after
t
threshold (near 1V) to protect voltage-sensitive output
devices. External pull-up resistors can augment the pull-up
current sources in case the leakage into the driving device is
greater than 30µA.
D3
FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE
. The pull-up current diminishes to zero above the logic
R
FB
EXTERNAL CIRCUIT
V
V
OUT
OUT
+
-
V
DROOP
C
R
REF
-
+
C
REGULATION WITH OFFSET ADJUSTMENT
R
C
REF
C
RGND
COMP
VDIFF
VSEN
DAC
REF
FB
ISL6336B
INTERNAL CIRCUIT
COMP
IAVG
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
ERROR AMPLIFIER
+
, is compared to the
-
+
-
V
August 31, 2010
COMP
DIFF
FN6696.2
, is