ISL6336BIRZ Intersil, ISL6336BIRZ Datasheet - Page 19

• Manufacturer Part Number: ISL6336BIRZ
• Description: IC CTRLR PWM SYNC BUCK 48-QFN
• Manufacturer: Intersil

Specifications of ISL6336BIRZ

• Applications: Controller, Intel VR11.1
• Voltage - Input: 3 ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.5 ~ 1.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dynamic VID
Modern microprocessors need to make changes to their
core voltage as part of the normal operation. They direct the
core-voltage regulator to do this by making changes to the
VID inputs during the regulator operation. The power
management solution is required to monitor the DAC inputs
and respond to on-the-fly VID changes in a controlled
manner. Supervising the safe output voltage transition within
the DAC range of the processor without discontinuity or
disruption is a necessary function of the core-voltage
regulator.
In order to ensure a smooth transition of output voltage
during VID change, a VID step change smoothing network,
composed of R
R
above in “Output-Voltage Offset Programming” on page 18.
The selection of C
VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at
1-bit every t
of R
During dynamic VID transition and VID up steps, the
overcurrent trip point increases by 140% to avoid false
triggering OCP circuits, while the overvoltage trip point is set
to its maximum VID OVP trip level. If dynamic VID occurs
when PSI# is asserted, the controller will activate all phases
and complete the transition at which point the status of the
PSI# pin will control operation.
C
REF
REF
FIGURE 7. OUTPUT VOLTAGE OFFSET PROGRAMMING
REF
⋅
is based on the desired offset voltage as detailed
R
and C
REF
1.6V
VID
=
VCC
+
REF
-
REF
, the relationship between the time constant
t
VID
REF
network and t
0.4V
and C
E/A
is based on the time duration for 1-bit
GND
+
+
+
-
-
-
REF
FB
19
+
, can be used. The selection of
-
VID
DYNAMIC
VID D/A
is given by Equation 13.
ISL6336B
OFS
DAC
GND
VCC
OR
(EQ. 13)
REF
R
R
C
OFS
REF
REF
ISL6336B
Operation Initialization
Prior to converter initialization, proper conditions must exist on
the enable inputs and VCC. When the conditions are met, the
controller begins soft-start. Once the output voltage is within the
proper window of operation, VR_RDY asserts logic high.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6336B
is released from shutdown mode.
1. The bias voltage applied at VCC must reach the internal
2. The ISL6336B features an enable input (EN_PWR) for
3. The voltage on EN_VTT must be higher than 0.875V to
FIGURE 8. POWER SEQUENCING USING THRESHOLD
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6336B is guaranteed. Hysteresis between the
rising and falling thresholds assure that once enabled,
the ISL6336B will not inadvertently turn off unless the
bias voltage drops substantially (see “Electrical
Specifications” table beginning on page 7).
power sequencing between the controller bias voltage and
another voltage rail. The enable comparator holds the
ISL6336B in shutdown until the voltage at EN_PWR rises
above 0.875V. The enable comparator has about 130mV
of hysteresis to prevent bounce. It is important that the
driver ICs reach their POR level before the ISL6336B
becomes enabled. The schematic in Figure 8
demonstrates sequencing the ISL6336B with the ISL66xx
family of Intersil MOSFET drivers, which require 12V bias.
enable the controller. This pin is typically connected to the
output of the VTT voltage regulator.
FAULT LOGIC
SOFT-START
CIRCUIT
POR
ISL6336B INTERNAL CIRCUIT
AND
SENSITIVE ENABLE (EN) FUNCTION
COMPARATOR
ENABLE
+
-
0.875V
+
-
0.875V
EXTERNAL CIRCUIT
VCC
EN_VTT
EN_PWR
100kΩ
9.1kΩ
+12V
August 31, 2010
FN6696.2