FAN5018BMTCX Fairchild Semiconductor, FAN5018BMTCX Datasheet - Page 16

• Manufacturer Part Number: FAN5018BMTCX
• Description: IC CTRLR DC-DC MULTIPH 28TSSOP
• Manufacturer: Fairchild Semiconductor

Specifications of FAN5018BMTCX

• Applications: Controller, High-Current, Implementing Low-Voltage CPU Core Power Circuits
• Voltage - Input: 12V
• Number Of Outputs: 1
• Voltage - Output: 0.5 ~ 3.5 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FAN5018B
amplifier, and a filter capacitor is placed in parallel with this
resistor. The amplifier’s gain is programmable by adjusting
the feedback resistor to set the load line required by the
microprocessor. The current information is then given as the
difference of CSREF –CSCOMP. This difference signal is
used internally to offset the VID DAC for voltage position-
ing and as a differential input for the current limit compara-
tor.
To provide the best accuracy for the current sensing, the
CSA is designed to have a low offset input voltage. Also,
external resistors determine the sensing gain so that it can be
made extremely accurate and flexible.
Active Impedance Control Mode
For controlling the output voltage droop as a function of
output current, the current sense amplifier (CSA) creates a
voltage signal proportional to the total inductor currents.
External components determine the ratio of this voltage to
the output current to allow it to be adjusted to set the
required load line. Inside the chip the CSA output voltage is
subtracted from the DAC voltage which then is used for the
reference to the error amplifier. As the output current
increases the reference to the error amp decreases causing
the output voltage to decrease accordingly.
Current Control Mode and Thermal Balance
The FAN5018B has individual inputs for each phase which
are used for monitoring the current in each phase. This infor-
mation is combined with an internal ramp to create a current
balancing feedback system that is optimized for initial cur-
rent balance accuracy and dynamic thermal balancing during
operation. This current balance information is independent
of the average output current information used for position-
ing described previously.
The magnitude of the internal ramp can be set to optimize
the transient response of the system. It also monitors the sup-
ply voltage for feed-forward control for changes in the sup-
ply. A resistor connected from the power input voltage to the
RAMPADJ pin determines the slope of the internal PWM
ramp. Detailed information about programming the ramp is
given in the Application Information section.
External resistors can be placed in series with individual
phases to create an intentional current imbalance if desired,
such as when one phase may have better cooling and can
support higher currents. Resistors R
(see the typical application circuit in Figure 4) can be used
for adjusting FET thermal and current balance. Zero ohm
placeholder resistors should be provided in the initial layout
to allow the phase balance to be adjusted during design fine
tuning.
To increase the current in any given phase, make R
that phase larger (make R
16
SW
= 0 for the hottest phase and do
SW1
through R
SW4
SW
for
not change during balancing). Increasing R
will substantially increase the phase current. Increase each
R
starting with the coolest phase first.
Voltage Control Mode
The voltage-mode control loop uses a high gain-bandwidth
voltage mode error amplifier. The control input voltage to
the positive input is set via the VID 6-bit logic code, accord-
ing to the voltages listed in Table 1. This voltage is also off-
set by the droop voltage for active positioning of the output
voltage as a function of current, commonly known as active
voltage positioning. The output of the amplifier is the COMP
pin, which sets the termination voltage for the internal PWM
ramps.
The negative input (F
with a resistor R
output voltage at this point. A current source from the F
flowing through R
voltage from the VID voltage. The no-load voltage will be
negative with respect to the VID DAC. The main loop com-
pensation is incorporated in the feedback network between
FB and COMP.
Soft-Start
The power-on ramp up time of the output voltage is set with
a capacitor and resistor in parallel from the DELAY pin to
ground. The RC time constant also determines the current
limit latch off time as explained in the following section. In
UVLO or when EN is a logic low, the DELAY pin is held at
ground. After the UVLO threshold is reached and EN is a
logic high, the DELAY cap is charged up with an internal
20µA current source. The output voltage follows the ramp-
ing voltage on the DELAY pin, limiting the inrush current.
The soft-start time depends on the value of VID DAC and
C
cation Information section for detailed information on set-
ting C
If EN is taken low or VCC drops below UVLO, the DELAY
cap is reset to ground to be ready for another soft start cycle.
Figure 1 shows a typical start-up sequence for the
FAN5018B.
Over Current Limit and Latch-off Protection
The FAN5018B compares a programmable current limit set
point to the voltage from the output of the current sense
amplifier. The level of current limit is set with the resistor
from the ILIMIT pin to ground. During normal operation,
the voltage on ILIMIT is 3V. The current through the exter-
nal resistor is internally scaled to give a current limit thresh-
old of approximately 10.4mV/µA. If the difference in
voltage between CSREF and CSCOMP rises above the cur-
rent limit threshold, the internal current limit amplifier will
control the internal COMP voltage to maintain the average
output current at the limit.
SW
DLY
value by small amounts to achieve balance,
, with a secondary effect from R
DLY
.
B
and is used for sensing and controlling the
B
is used for setting the no-load offset
B
) is tied to the output sense location
PRODUCT SPECIFICATION
DLY
REV. 1.0.0 Jul/15/05
. Refer to the Appli-
SW
to only 500
B
pin
Ω