FAN5018BMTCX Fairchild Semiconductor, FAN5018BMTCX Datasheet - Page 18

• Manufacturer Part Number: FAN5018BMTCX
• Description: IC CTRLR DC-DC MULTIPH 28TSSOP
• Manufacturer: Fairchild Semiconductor

Specifications of FAN5018BMTCX

• Applications: Controller, High-Current, Implementing Low-Voltage CPU Core Power Circuits
• Voltage - Input: 12V
• Number Of Outputs: 1
• Voltage - Output: 0.5 ~ 3.5 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FAN5018B
Power Good Monitoring
The Power Good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open drain output
whose high level (when connected to a pull-up resistor) indi-
cates that the output voltage is within the nominal limits
specified in the specifications table based on the VID voltage
setting. PWRGD will go low if the output voltage is outside
of this specified range. PWRGD is blanked during a VID
OTF event for a period of 250µs to prevent false signals dur-
ing the time the output is changing.
Output Crowbar
As part of the protection for the load and output components
of the supply, the PWM outputs will be driven low (turning
on the low-side MOSFETs) when the output voltage exceeds
the upper Power Good threshold. This crowbar action will
stop once the output voltage has fallen below the release
threshold of approximately 550mV.
Turning on the low-side MOSFETs pulls down the output
voltage as the reverse current builds up in the inductors.
If the output overvoltage is due to a short of the high-side
MOSFET, this action will current limit the input supply
or blow its fuse, protecting the microprocessor from
destruction.
Output Enable and UVLO
The input supply (VCC) to the controller must be higher than
the UVLO threshold and the EN pin must be higher then its
logic threshold for the FAN5018B to begin switching. If
UVLO is less than the threshold or the EN pin is a logic low,
the FAN5018B is disabled. This holds the PWM outputs at
ground, shorts the DELAY capacitor to ground, and holds
the ILIMIT pin at ground.
In the application circuit, the ILIMIT pin should be con-
nected to the output disable pins of the FAN5009 drivers.
Because ILIMIT is grounded, this disables the drivers such
that both DRVH and DRVL are grounded. This feature is
important to prevent discharging of the output capacitors
when the controller is shut off. If the driver outputs were not
disabled, then a negative voltage could be generated on the
output due to the high current discharge of the output
capacitors through the inductors.
18
Application Information
The design parameters for a typical Intel VRD10.x-compli-
ant CPU application are as follows:
• Input voltage (V
• VID setting voltage (V
• Duty cycle (D) = 0.125
• Nominal output voltage at no load (V
• Nominal output voltage at 65A load (V
• Static output voltage drop based on a 1.3 m
• (V
• Maximum output current (I
• Maximum output current step (ΔI
• Number of phases (n) = 3
• Switching frequency per phase (f
Setting the Clock Frequency
The FAN5018B uses a fixed-frequency control architecture
with the frequency being set by an external timing resistor
(R
mine the switching frequency per phase, which relates
directly to switching losses and the sizes of the inductors and
input and output capacitors. With n = 3 for three phases, a
clock frequency of 684kHz sets the switching frequency of
each phase, f
trade-off between the switching losses and the sizes of the
output filter components. TPC 1 shows that to achieve a
684kHz oscillator frequency, the correct value for R
301k
using:
where 5.0pF and 110nS are internal IC component values.
For good initial accuracy and frequency stability, it is recom-
mended to use a 1% resistor.
Soft-Start and Current Limit Latch-Off Delay
Times
Because the soft-start and current limit latch off delay
functions share the DELAY pin, these two parameters must
be considered together. The first step is to set C
soft-start ramp. This ramp is generated with a 20µA internal
current source. The value of R
impact on the soft-start time because it sinks part of the cur-
rent source to ground. However, as long as R
greater than 200k
can be approximated using:
R
T
T
(R
). The clock frequency and the number of phases deter-
=
Ω
O
D
(
. Alternatively, the value for R
) from no load to full load
) = V
n
×
f
SW
ONL
SW
×
, to 228kHz, which represents a practical
5
– V
1
Ω
pF
, this effect is minor. The value for C
IN
OFL
)
) = 12V
−
110
= 1.480V – 1.3955V = 84.5mV
VID
nS
) = 1.500V
O
DLY
) = 65A
PRODUCT SPECIFICATION
will have a second order
SW
O
T
) = 60A
) = 228 kHz
can be calculated
ONL
REV. 1.0.0 Jul/15/05
OFL
) = 1.480V
DLY
) = 1.3955V
Ω
DLY
load line
is kept
T
for the
is
DLY
(1)