FAN5018BMTCX Fairchild Semiconductor, FAN5018BMTCX Datasheet - Page 6

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FAN5018BMTCX

Manufacturer Part Number
FAN5018BMTCX
Description
IC CTRLR DC-DC MULTIPH 28TSSOP
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of FAN5018BMTCX

Applications
Controller, High-Current, Implementing Low-Voltage CPU Core Power Circuits
Voltage - Input
12V
Number Of Outputs
1
Voltage - Output
0.5 ~ 3.5 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FAN5018BMTCX
Manufacturer:
SERVERWOR
Quantity:
400
Part Number:
FAN5018BMTCX(5018BMTC)
Manufacturer:
ST
Quantity:
20 000
FAN5018B
Electrical Specifications
(V
The • denotes specifications which apply over the full operating temperature range.
Notes:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control
2. Guaranteed by design – NOT tested in production.
6
Parameter
DC Gain
Input Common Mode
Range
Positioning Accuracy
Output Voltage Range
Output Current
Current Balance Circuit
Input Operating Range
Input Resistance
Input Current
Input Current Matching
Current Limit Comparator
ILIMIT Output Voltage
Output Current, Normal
Mode
Maximum Output Current
Current Limit Threshold
Voltage
Current Limit Setting Ratio
Latch-off Delay Threshold
Latch-off Delay Time
Soft Start
Output Current,
Soft start Mode
Soft Start Delay Time
Enable Input
Input Low Voltage
Input High Voltage
Input Current, EN Low
Input Current, EN High
Power Good Comparator
Under voltage Threshold
Over voltage Threshold
Output Low Voltage
CC
Normal Mode
In Shutdown
= 12V, T
A
= 0°C to +85°C and FBRTN=GND, using circuit in Figure 1, unless otherwise noted.)
V
ΔV
I
V
R
I
ΔI
V
V
I
V
t
I
T
V
V
I
I
V
V
V
O(CSA)
SW(X)
ILIMIT(NM)
DELAY
DELAY(SS)
IL(EN)
IH(EN)
DELAY(SS)
SW(X)CM
ILIMIT(NM)
ILIMIT(SD)
CL
DELAY
IL(EN)
IH(EN)
PWRGD(UV)
PWRGD(OV)
OL(PWRGD)
SW(X)
SW(X)
Symbol
FB
(continued)
( See Note 2)
CSSUM and CSREF
COMP = FB, Test Circuit 2
I
FB forced to V
SW(X) = 0V
SW(X) = 0V
SW(X) = 0V
R
I
R
V
V
V
In Current Limit
R
During Start-up, DELAY < 2.8V
R
VID = 011111 (1.475V)
EN = 0V
EN = 1.25V
Relative to DAC Output
Relative to DAC Output
I
CSCOMP
ILIMIT
PWRGD(SINK)
IILIMIT
CSREF
CL
ILIMIT
ILIMIT
DELAY
DELAY
/I
ILIMIT
= -100µA
= 250kΩ
= 250kΩ
= 3V
–V
= 250kΩ, C
= 250kΩ, C
= ±100µA
CSCOMP
= 4mA
Conditions
OUT
, R
– 3% Source/Sink
DELAY
DELAY
ILIMIT
= 4.7nF
= 4.7nF,
= 250kΩ
Min.
-600
-325
300
105
180
-84
0.1
-10
2.9
1.7
-25
0.8
20
60
-5
-1
0
PRODUCT SPECIFICATION
Typ.
-250
10.4
375
125
600
400
300
225
-80
-20
1.8
77
30
12
10
-7
3
REV. 1.0.0 Jul/15/05
Max.
+200
-200
400
150
400
400
-76
-15
3.3
3.1
1.9
0.4
+5
40
25
-4
3
1
mV/µA
Units
mV
mV
mV
mV
mV
mV
mV
dB
µA
µA
µA
µA
µA
µA
µA
µs
µs
%
V
V
V
V
V
V

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