MAX17082GTL+ Maxim Integrated Products, MAX17082GTL+ Datasheet - Page 32

• Manufacturer Part Number: MAX17082GTL+
• Description: IC CTLR PWM DUAL IMVP-6.5 40TQFN
• Manufacturer: Maxim Integrated Products
• Series: Quick-PWM™r

Specifications of MAX17082GTL+

• Applications: Controller, Intel IMVP-6.5™
• Voltage - Input: 4.5 ~ 5.5 V
• Number Of Outputs: 1
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Lead Free Status / Rohs Status: Details

Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
When the processor enters low-power deeper sleep
mode, the IMVP-6 CPU sets the VID DAC code to a
lower output voltage and drives DPRSLPVR high. The
MAX17021/MAX17082/MAX17482 respond by slewing
the internal target voltage to the new DAC code, switch-
ing to single-phase operation, and letting the output
voltage gradually drift down to the deeper sleep volt-
age. During the transition, the MAX17021/MAX17082/
MAX17482 blank both the upper and lower PWRGD
and CLKEN thresholds until 20μs after the internal tar-
get reaches the deeper sleep voltage. Once the 20μs
timer expires, the MAX17021/MAX17082/MAX17482
reenable the lower PWRGD and CLKEN threshold, but
keep the upper threshold blanked until the output volt-
age reaches the regulation level. PHASEGD remains
blanked high impedance while DPRSLPVR is high.
The MAX17021/MAX17082/MAX17482 perform mode
transitions in a controlled manner, automatically mini-
mizing input surge currents. This feature allows the cir-
cuit designer to achieve nearly ideal transitions,
guaranteeing just-in-time arrival at the new output-volt-
age level with the lowest possible peak currents for a
given output capacitance.
At the beginning of an output-voltage transition, the
MAX17021/MAX17082/MAX17482 blank both PWRGD
thresholds, preventing the PWRGD open-drain output
from changing states during the transition. The con-
troller enables the lower PWRGD threshold approxi-
mately 20μs after the slew-rate controller reaches the
target output voltage, but the upper PWRGD threshold
remains blanked until the output voltage reaches the
regulation level if the controller enters pulse-skipping
operation. The slew rate (set by resistor R
set fast enough to ensure that the transition can be
completed within the maximum allotted time.
The MAX17021/MAX17082/MAX17482 automatically
control the current to the minimum level required to
complete the transition in the calculated time. The slew-
rate controller uses an internal capacitor and current
source programmed by R
voltage. The total transition time depends on R
voltage difference, and the accuracy of the slew-rate
controller (C
dependent on the total output capacitance, as long as
the surge current is less than the current limit. For all
32
______________________________________________________________________________________
Output-Voltage-Transition Timing
SLEW
accuracy). The slew rate is not
TIME
to transition the output
Suspend Mode
TIME
) must be
TIME
, the
dynamic VID transitions, the transition time (t
given by:
where dV
slew rate, V
is the new target voltage. See TIME Slew Rate
Accuracy in Electrical Characteristics for slew-rate lim-
its. For soft-start and shutdown, the controller automati-
cally reduces the slew rate to 1/8.
The output voltage tracks the slewed target voltage,
making the transitions relatively smooth. The average
inductor current per phase required to make an output-
voltage transition is:
where dV
the total output capacitance, and η
of active phases.
When DPRSLPVR goes high, the MAX17021/MAX17082/
MAX17482 immediately disable phase 2 (DH2 and DL2
forced low), blank PHASEGD high impedance, and enter
pulse-skipping operation (see Figures 5 and 6). If the
VIDs are set to a lower voltage setting, the output drops
at a rate determined by the load and the output capaci-
tance. The internal target still ramps as before, and
PWRGD remains blanked high impedance until 20μs
after the output voltage reaches the internal target.
• Fast C4E Deeper Sleep Exit: When exiting deeper
sleep (DPRSLPVR pulled low) while the output volt-
age still exceeds the deeper sleep voltage, the
MAX17021/MAX17082/MAX17482 quickly slew
(50mV/μs min regardless of R
nal target voltage to the DAC code provided by the
processor as long as the output voltage is above the
new target. The controller remains in skip mode until
the output voltage equals the internal target. Once
the internal target reaches the output voltage, phase
2 is enabled. The controller blanks PWRGD,
PHASEGD, and CLKEN until 20μs after the transition
is completed. See Figure 5.
TARGET
TARGET
OLD
t
TRAN
I
L
is the original output voltage, and V
/dt = 12.5mV/μs x 71.5kΩ/R
/dt is the required slew rate, C
≅
η
=
C
TOTAL
OUT
(
dV
V
NEW
TARGET
×
Deeper Sleep Transitions
-
(
dV
V
OLD
TARGET
TIME
dt
TOTAL
)
setting) the inter-
dt
is the number
)
TIME
TRAN
OUT
is the
NEW
) is
is