MAX17082GTL+ Maxim Integrated Products, MAX17082GTL+ Datasheet - Page 45

• Manufacturer Part Number: MAX17082GTL+
• Description: IC CTLR PWM DUAL IMVP-6.5 40TQFN
• Manufacturer: Maxim Integrated Products
• Series: Quick-PWM™r

Specifications of MAX17082GTL+

• Applications: Controller, Intel IMVP-6.5™
• Voltage - Input: 4.5 ~ 5.5 V
• Number Of Outputs: 1
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Lead Free Status / Rohs Status: Details

the current limit and cause the fault latch to trip. To pro-
tect against this possibility, you can over design the cir-
cuit to tolerate:
where I
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good-size heatsink to handle the overload
power dissipation.
Choose a Schottky diode (D
low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. Select a
diode that can handle the load current per phase dur-
ing the dead times. This diode is optional and can be
removed if efficiency is not critical.
The boost capacitors (C
enough to handle the gate-charging requirements of
the high-side MOSFETs. Typically, 0.1μF ceramic
capacitors work well for low-power applications driving
medium-sized MOSFETs. However, high-current appli-
cations driving large, high-side MOSFETs require boost
capacitors larger than 0.1μF. For these applications,
select the boost capacitors to avoid discharging the
capacitor more than 200mV while charging the high-
side MOSFETs’ gates:
where N is the number of high-side MOSFETs used for
one regulator, and Q
in the MOSFET’s data sheet. For example, assume (2)
IRF7811W n-channel MOSFETs are used on the high
side. According to the manufacturer’s data sheet, a sin-
gle IRF7811W has a maximum gate charge of 24nC
(V
boost capacitance would be:
Selecting the closest standard value, this example
requires a 0.22μF ceramic capacitor.
GS
= 5V). Using the above equation, the required
I
LOAD
VALLEY(MAX)
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
=
=
η
η
C
TOTAL VALLEY MAX
TOTAL VALLEY MAX
BST_
C
______________________________________________________________________________________
BST
GATE
=
I
Dual-Phase, Quick-PWM Controllers for
⎛
⎝ ⎜
is the maximum valley current
_
I
2 24
200
=
×
BST_
N Q
is the gate charge specified
mV
×
200
(
nC
L
) must be selected large
(
) with a forward voltage
GATE
mV
=
Boost Capacitors
)
0 24
+
)
.
+
⎛
⎜
⎝
I
LOAD MAX
Δ
μF
I
INDUCTOR
(
2
2
)
L L IR
⎞
⎠ ⎟
⎞
⎟
⎠
The current-balance compensation capacitor (C
integrates the difference between the main and sec-
ondary current-sense voltages. The internal compensa-
tion resistor (R
response by increasing the phase margin. This allows
the dynamics of the current-balance loop to be opti-
mized. Excessively large capacitor values increase the
integration time constant, resulting in larger current dif-
ferences between the phases during transients.
Excessively small capacitor values allow the current
loop to respond cycle-by-cycle, but can result in small
DC current variations between the phases. For most
applications, a 470pF capacitor from CCI to the switch-
ing regulator’s output works well.
Connecting the compensation network to the output
(V
voltage signal, especially during transients.
Voltage positioning dynamically lowers the output volt-
age in response to the load current, reducing the out-
put capacitance and processor’s power-dissipation
requirements. The controller uses a transconductance
amplifier to set the transient and DC output-voltage
droop (Figure 3) as a function of the load. This adjusta-
bility allows flexibility in the selected current-sense
resistor value or inductor DCR, and allows smaller cur-
rent-sense resistance to be used, reducing the overall
power dissipated.
Connect a resistor (R
the DC steady-state droop (load line) based on the
required voltage-positioning slope (R
where the effective current-sense resistance (R
depends on the current-sense method (see the Current
Sense section), and the voltage-positioning amplifier’s
transconductance (G
defined in the Electrical Characteristics table. The con-
troller sums together the input signals of the current-
sense inputs (CSP_, CSN_).
When the inductors’ DCR is used as the current-sense
element (R
should include an NTC thermistor to minimize the tem-
perature dependence of the voltage-positioning slope.
OUT
) allows the controller to feed-forward the output-
Current-Balance Compensation (CCI)
SENSE
CCI
R
= R
FB
Steady-State Voltage Positioning
FB
=
= 200kΩ) improves transient
DCR
R
) between FB and V
m(FB)
Voltage Positioning and
SENSE m FB
R
), each current-sense input
DROOP
Loop Compensation
) is typically 600μS as
G
(
DROOP
)
):
OUT
SENSE
to set
CCI
45
)
)