MAX17082GTL+ Maxim Integrated Products, MAX17082GTL+ Datasheet - Page 47

• Manufacturer Part Number: MAX17082GTL+
• Description: IC CTLR PWM DUAL IMVP-6.5 40TQFN
• Manufacturer: Maxim Integrated Products
• Series: Quick-PWM™r

Specifications of MAX17082GTL+

• Applications: Controller, Intel IMVP-6.5™
• Voltage - Input: 4.5 ~ 5.5 V
• Number Of Outputs: 1
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Lead Free Status / Rohs Status: Details

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1) Place the power components first, with ground ter-
2) Mount the controller IC adjacent to the low-side
PROCESS: BiCMOS
Keep the high-current, gate-driver traces (DL_,
DH_, LX_, and BST_) short and wide to minimize
trace resistance and inductance. This is essential
for high-power MOSFETs that require low-imped-
ance gate drivers to avoid shoot-through currents.
CSP_ and CSN_ connections for current limiting
and voltage positioning must be made using Kelvin-
sense connections to guarantee the current-sense
accuracy.
When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
Route high-speed switching nodes away from sen-
sitive analog areas (CCI, FB, CSP_, CSN_, etc.).
minals adjacent (low-side MOSFET source, C
C
connections on the top layer with wide, copper-
filled areas.
MOSFET. The DL_ gate traces must be short and
wide (50 mils to 100 mils wide if the MOSFET is 1in
from the controller IC).
OUT
, and D1 anode). If possible, make all these
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Chip Information
Layout Procedure
IN
,
3) Group the gate-drive components (BST_ diodes
4) Make the DC-DC controller ground connections as
5) Connect the output power planes (V
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE
and capacitors, V
near the controller IC.
shown in Figures 1 and 2. This diagram can be
viewed as having four separate ground planes:
input/output ground, where all the high-power com-
ponents go; the power ground plane, where the
GND pin and V
ter’s analog ground plane where sensitive analog
components go, the master’s GND pin and V
bypass capacitor go; and the slave’s analog
ground plane where the slave’s GND pin and V
bypass capacitor go. The master’s GND plane must
meet the GND plane only at a single point directly
beneath the IC. Similarly, the slave’s GND plane
must meet the GND plane only at a single point
directly beneath the IC. The respective master and
slave ground planes should connect to the high-
power output ground with a short metal trace from
GND to the source of the low-side MOSFET (the
middle of the star ground). This point must also be
very close to the output capacitor ground terminal.
tem ground planes) directly to the output filter
capacitor positive and negative terminals with multi-
ple vias. Place the entire DC-DC converter circuit as
close to the CPU as is practical.
40 TQFN-EP
PACKAGE CODE
DD
Package Information
DD
bypass capacitor go; the mas-
T4055-2
bypass capacitor) together
DOCUMENT NO.
CORE
21-0140
and sys-
CC
CC
47