L6701 STMicroelectronics, L6701 Datasheet - Page 24

• Manufacturer Part Number: L6701
• Description: IC CTRLR 3PH VR10/9/K8 PWRSO-36
• Manufacturer: STMicroelectronics

Specifications of L6701

• Applications: Controller, Intel VR9, VR10, K8
• Voltage - Input: 12V
• Number Of Outputs: 3
• Voltage - Output: 0.8 ~ 1.85 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 36-PowerSOIC
• Output Voltage: 0.8 V to 1.85 V
• Output Current: 1.5 A
• Switching Frequency: 110 KHz
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10 Output Voltage Positioning
10.3
Caution:
10.4
24/44
Table 9.
Offset (Optional)
Positive offset can be added to the programmed reference by connecting a R
between the REF_OUT and REF_IN pins. Referring to
(I
programming a fixed voltage drop across R
reference giving the desired offset to the output voltage as follow:
Offset current is suddenly sourced from REF_IN pin as soon as the device implements Soft-
Start: to avoid having steps during soft-start, the introduction of C
required. The resulting time constant need to be negligible with respect to the soft-start time as
well as long enough to smooth the initial step. Typical values are in the range of few hundreds
of nF.
Offset function can be easily disabled simply setting R
Offset automatically given by the DAC selection differs from the offset implemented through the
OFFSET pin: the built-in feature is trimmed in production and assures ±0.7% accuracy over
load and line variations.
Remote Voltage Sense
L6701 embeds a Remote Sense Buffer to sense remotely the regulated voltage without any
additional external components. In this way, the output voltage programmed is regulated
between the remote buffer inputs compensating motherboard or connector losses. The device
senses the output voltage remotely through the pins FBR and FBG (FBR is for the regulated
voltage sense while FBG is for the ground sense) and reports this voltage internally at VSEN
pin with unity gain eliminating the errors. Keeping the FBR and FBG traces parallel and
guarded by a power plane results in common mode coupling for any picked-up noise.
Layout-insensitive BOM
Time-Constant Matching
R
R
R
OS
D
FB
LL
Design (given OCP th.)
=11.5µA) is sourced from the REF_IN pin as soon as the device is enabled, so
(given R
Design (given R
Comparison between different load-line implementations.
D
and R
LL
FB
)
)
R
------------ -
DCR
Fully-Differential LL
R
R
LL
V
L
D
FB
O S
=
=
OS
=
3
=
=
OCP
: this voltage is directly added to the programmed
R
--------- -
⋅
R
R
Y
3
DCR
------------ - R
LL
R
PH
OS
D
⋅
⋅
⋅
DCR
------------ -
------------ -
DCR
⋅
35µ
C
R
⋅
I
OS
D
PH
OS
Figure
FB
= 0.
7, a constant current
OS
Non-Fully-Differential LL
(in parallel to R
------------ -
DCR
R
R
R
L
D
FB
LL
=
=
=
=
OCP
------------ -
DCR
------------ - R
R
OS
R
-------------------------- -
3
R
N
L L
PH
D
resistor
⋅
⋅
3
⋅
------------ -
DCR
⋅
DCR
------------ -
35µ
OS
R
C
D
FB
PH
) is
L6701