LTC1871EMS-7 Linear Technology, LTC1871EMS-7 Datasheet - Page 27

• Manufacturer Part Number: LTC1871EMS-7
• Description: IC MULTI CONFIG SYNC ADJ 10MSOP
• Manufacturer: Linear Technology
• Type: Step-Up (Boost), Flyback, Sepicr

Specifications of LTC1871EMS-7

• Internal Switch(s): No
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 1.23 ~ 36 V
• Current - Output: 50mA
• Frequency - Switching: 50kHz ~ 1MHz
• Voltage - Input: 6 ~ 36 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

APPLICATIONS INFORMATION
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
The R
the R
the board to the ambient temperature in the enclosure.
This value of T
assumption for the junction temperature in the iterative
calculation process.
SEPIC Converter: Output Diode Selection
To maximize effi ciency, a fast-switching diode with low
forward drop and low reverse leakage is desired. The output
diode in a SEPIC converter conducts current during the
switch off-time. The peak reverse voltage that the diode
must withstand is equal to V
forward current in normal operation is equal to the output
current, and the peak current is equal to:
The power dissipated by the diode is:
and the diode junction temperature is:
The R
the R
the board to the ambient temperature in the enclosure.
SEPIC Converter: Output Capacitor Selection
Because of the improved performance of today’s electro-
lytic, tantalum and ceramic capacitors, engineers need
to consider the contributions of ESR (equivalent series
resistance), ESL (equivalent series inductance) and the
bulk capacitance when choosing the correct component
for a given output ripple voltage. The effects of these three
T
P
T
I
D(PEAK)
J
J
D
TH(JC)
TH(JC)
= T
= T
TH(JA)
TH(JA)
= I
A
O(MAX)
A
+ P
+ P
for the device plus the thermal resistance from
for the device plus the thermal resistance from
= 1+
to be used in this equation normally includes
to be used in this equation normally includes
FET
D
J
• R
• V
can then be used to check the original
•R
2
TH(JA)
D
TH(JA)
•I
O(MAX)
IN(MAX)
•
V
V
IN(MIN)
O
+ V
+ V
D
O
+ 1
. The average
parameters (ESR, ESL, and bulk C) on the output voltage
ripple waveform are illustrated in Figure 21 for a typical
coupled-inductor SEPIC converter.
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step and the charging/discharging ΔV.
For the purpose of simplicity we will choose 2% for the
maximum output ripple, to be divided equally between the
ESR step and the charging/discharging ΔV. This percentage
ripple will change, depending on the requirements of the
application, and the equations provided below can easily
be modifi ed.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor can be determined using the fol-
lowing equation:
where:
For the bulk C component, which also contributes 1% to
the total ripple:
For many designs it is possible to choose a single capacitor
type that satisfi es both the ESR and bulk C requirements
for the design. In certain demanding applications, however,
the ripple voltage can be improved signifi cantly by con-
necting two or more types of capacitors in parallel. For
example, using a low ESR ceramic capacitor can minimize
the ESR step, while an electrolytic or tantalum capacitor
can be used to supply the required bulk C.
Once the output capacitor ESR and bulk capacitance have
been determined, the overall ripple voltage waveform
ESR
I
C
D(PEAK)
OUT
COUT
0.01• V
= 1+
I
O(MAX)
0.01• V
I
D(PEAK)
2
O
• f
•I
O
O(MAX)
•
V
V
IN(MIN)
O
LTC1871-7
+ V
D
+ 1
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