LTC1709EG#TRPBF Linear Technology, LTC1709EG#TRPBF Datasheet - Page 20

• Manufacturer Part Number: LTC1709EG#TRPBF
• Description: IC SW REG STEP-DOWN SYNC 36-SSOP
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LTC1709EG#TRPBF

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 1.3 ~ 3.5 V
• Current - Output: 3A
• Voltage - Input: 4 ~ 36 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Frequency - Switching: -

APPLICATIO S I FOR ATIO
LTC1709
applications may approach this minimum on-time limit
and care should be taken to ensure that:
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC1709 will begin to skip
cycles resulting in variable frequency operation. The out-
put voltage will continue to be regulated, but the ripple
current and ripple voltage will increase.
The minimum on-time for the LTC1709 is generally less
than 200ns. However, as the peak sense voltage de-
creases, the minimum on-time gradually increases. This is
of particular concern in forced continuous applications
with low ripple current at light loads. If the duty cycle drops
below the minimum on-time limit in this situation, a
significant amount of cycle skipping can occur with corre-
spondingly larger ripple current and voltage ripple.
If an application can operate close to the minimum on-
time limit, an inductor must be chosen that has a low
enough inductance to provide sufficient ripple amplitude
to meet the minimum on-time requirement. As a general
rule, keep the inductor ripple current of each phase equal
to or greater than 15% of I
Voltage Positioning
Voltage positioning can be used to minimize peak-to-peak
output voltage excursion under worst-case transient load-
ing conditions. The open-loop DC gain of the control loop
is reduced depending upon the maximum load step speci-
fication. Voltage positioning can easily be added to the
LTC1709 by loading the I
having a Thevenin equivalent voltage source equal to the
midpoint operating voltage of the error amplifier, or 1.2V
(see Figure 8).
The resistive load reduces the DC loop gain while main-
taining the linear control range of the error amplifier. The
worst-case peak-to-peak output voltage deviation due to
transient loading can theoretically be reduced to half or
alternatively the amount of output capacitance can be
reduced for a particular application. A complete explana-
20
t
ON MIN
V f
V
IN
OUT
U
U
TH
OUT(MAX)
pin with a resistive divider
W
at V
IN(MAX)
U
.
tion is included in Design Solutions 10 or the LTC1736
data sheet. (See www.linear-tech.com)
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1709 circuits: 1) I
MOSFET transition losses, 3) INTV
and 4) LTC1709 V
differential amplifier output).
1) I
fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous mode
the average output current flows through L and R
but is “chopped” between the topside MOSFET and the
synchronous MOSFET. If the two MOSFETs have approxi-
mately the same R
MOSFET can simply be summed with the resistances of L,
R
R
total resistance is 25m . This results in losses ranging
from 2% to 8% as the output current increases from 3A to
15A per output stage for a 5V output, or a 3% to 12% loss
per output stage for a 3.3V output. Efficiency varies as the
inverse square of V
SENSE
DS(ON)
Figure 8. Active Voltage Positioning Applied to the LTC1709
%Efficiency = 100% – (L1 + L2 + L3 + ...)
2
R losses are predicted from the DC resistances of the
and ESR to obtain I
=10m , R
INTV
CC
R
R
T2
T1
L
OUT
IN
=10m , and R
DS(ON)
current (including loading on the
for the same external components
R
C
C
C
2
, then the resistance of one
R losses. For example, if each
I
TH
LTC1709
2
R losses, 2) Topside
SENSE
CC
regulator current
1709 F08
=5m , then the
SENSE
,