ISL85033IRTZ-T Intersil, ISL85033IRTZ-T Datasheet - Page 2

• Manufacturer Part Number: ISL85033IRTZ-T
• Description: IC REG BUCK ADJ DUAL 28TQFN
• Manufacturer: Intersil
• Type: Step-Down (Buck)r

Specifications of ISL85033IRTZ-T

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 0.8 ~ 28 V
• Current - Output: 3A
• Frequency - Switching: 300kHz ~ 2MHz
• Voltage - Input: 4.5 ~ 28 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-WFQFN exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

Pin Descriptions
Pin Configuration
PIN NUMBER
6, 7, 15, 16
8, 9, 13, 14
10, 12
1, 21
2, 20
3, 19
4, 18
5, 17
11
23
PHASE1, PHASE2
COMP1, COMP2
PGND1, PGND2
BOOT1, BOOT2
VIN1, VIN2
SYNCOUT
SS1, SS2
EN1, EN2
SYMBOL
FB1, FB2
VCC
2
PHASE1
PHASE1
COMP1
PGND1
BOOT1
Synchronization output. Provides a signal that is the inverse of the SYNCIN signal.
COMP1/COMP2 is the output of the error amplifier.
Feedback pin for the regulator. FB is the negative input to the voltage loop error amplifier.
COMP is the output of the error amplifier. The output voltage is set by an external resistor
divider connected to FB.
In addition, the PWM regulator’s power-good and undervoltage protection circuits use
FB1/2 to monitor the regulator output voltage.
Soft-Start pins for each controller. The SS1/2 pins control the soft-start and sequence of
their respective outputs. A single capacitor from the SS pin to ground determines the
output ramp rate. See the “Output Tracking and Sequencing” on page 16 for soft-start and
output tracking/sequencing details. If SS pins are tied to VCC, an internal soft-start of 2ms
will be used.
Power ground connections. Connect directly to the system GND plane.
Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor
provides the necessary charge to turn on the internal N-Channel MOSFET. Connect an
external capacitor from this pin to PHASE.
Switch node output. It connects the source of the internal power MOSFET with the external
output inductor and with the cathode of the external diode.
The input supply for the power stage of the PWM regulator and the source for the internal
linear regulator that provides bias for the IC. Place a minimum of 10µF ceramic capacitance
from each VIN to GND and close to the IC for decoupling.
PWM controller’s enable inputs. The PWM controllers are held off when the pin is pulled to
ground. When the voltage on this pin rises above 2V, the PWM controller is enabled.
Output of the internal 5V linear regulator. Decouple to PGND with a minimum of 4.7µF
ceramic capacitor.
FB1
SS1
1
2
3
4
5
6
7
28
8
27
9
ISL85033
ISL85033
(28 LD TQFN)
26
ISL85033
10
TOP VIEW
25
PD
11
24
12
23
13
PIN DESCRIPTION
22
14
21
20
19
18
17
16
15
COMP2
FB2
SS2
PGND2
BOOT2
PHASE2
PHASE2
December 8, 2010
FN6676.2