MC33167D2T ON Semiconductor, MC33167D2T Datasheet - Page 16

IC REG SWITCH INVERT 5A D2PAK-5

MC33167D2T

Manufacturer Part Number
MC33167D2T
Description
IC REG SWITCH INVERT 5A D2PAK-5
Manufacturer
ON Semiconductor
Type
Step-Down (Buck), Step-Up (Boost), Invertingr
Datasheet

Specifications of MC33167D2T

Internal Switch(s)
Yes
Synchronous Rectifier
No
Number Of Outputs
1
Voltage - Output
5 ~ 40 V
Current - Output
5A
Frequency - Switching
72kHz
Voltage - Input
7.5 ~ 40 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
D²Pak, TO-263 (5 leads + tab)
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power - Output
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC33167D2T
Manufacturer:
ON
Quantity:
347
Part Number:
MC33167D2T
Manufacturer:
MOT
Quantity:
5 510
Part Number:
MC33167D2TC
Quantity:
5 510
Part Number:
MC33167D2TC
Manufacturer:
TI
Quantity:
5 510
The following converter characteristics must be chosen:
1. V
2. V
3. Duty cycle is calculated at the minimum operating input voltage and must not exceed the guaranteed minimum DC
V
ripple(pp)
sat
F
Calculation
(Notes 1, 2)
Duty Cycle
V
− Output rectifier forward voltage drop. Typical value for 1N5822 Schottky barrier rectifier is 0.35 V.
DI
V
I
I
(Note 3)
out
out
pk(switch)
− Switch Output source saturation voltage, refer to Figure 8.
ripple(pp)
I
L
L avg
V
t on
t off
t
on
L
out
Desired output voltage.
Desired output current.
Desired peak−to−peak inductor ripple current. For maximum output current especially when the duty cycle is greater than 0.5,
it is suggested that DI
value, let DI
Desired peak−to−peak output ripple voltage. For best performance, the ripple voltage should be kept to less than 2% of V
Capacitor C
DI L
L
O
= 2 (I
should be a low equivalent series resistance (ESR) electrolytic designed for switching regulator applications.
V in * V sat * V out
V in * V sat * V out
f osc
I L avg )
V ref
8f osc C o
L avg
Step−Down
V out ) V F
L
t
DI L
1
on
be chosen minimum current limit threshold of 5.5 A. If the design goal is to use a minimum inductance
). This will proportionally reduce the converter’s output current capability.
t on
t off
I
R 2
R 1
t on
t off
out
f
osc
) 1
) 1
2 ) (ESR) 2
DI L
2
t on
Table 1. Design Equations
MC34167, MC33167
http://onsemi.com
t on
t off
V in * V satQ1 * V satQ2
) 1
V in * V satQ1 * V satQ2
V out ) V F1 ) V F2
16
Step−Up/Down
f osc
I L avg )
I out
V ref
t
DI L
on
f osc C o
t on
t off
t on
t off
t on
t off
R 2
R 1
f
1
osc
) 1
) 1
) 1
DI L
2
2 ) (ESR) 2
t on
t on
t off
) 1
Voltage−Inverting
I L avg )
f osc
V in * V sat
V ref
I out
|V out | ) V F
V in * V sat
(max)
t
DI L
on
f osc C o
t on
t off
t on
t off
R 2
R 1
t on
t off
f
1
osc
specification of 0.92.
) 1
) 1
) 1
DI L
2
t on
2 ) (ESR) 2
out
.

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