DS1865T+ Maxim Integrated Products, DS1865T+ Datasheet - Page 16

• Manufacturer Part Number: DS1865T+
• Description: IC PON TRIPLEXER CTRLR 28TQFN-EP
• Manufacturer: Maxim Integrated Products

Specifications of DS1865T+

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 28-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PON Triplexer Control and
Monitoring Circuit
Table 5. FETG, MOD, and BIAS Outputs
as a Function of TX-D and Alarm Sources
the first SEE recall, but the device analog is shut down
and the outputs are disabled. FETG is driven to its
alarm state defined by the FETG DIR bit (Table 02h,
Register 89h). If the supply voltage recovers back
above V
functioning. If the supply voltage falls below V
device SRAM is placed in its default state and another
SEE recall is required to reload the nonvolatile settings.
The EEPROM recall occurs the next time V
V
voltage varies.
Any time V
used to determine if V
accomplished by checking the RDYB bit in the status
(Lower Memory, Register 6Eh) byte. RDYB is set when
V
is timed (within 500µs) to go to 0, at which point the part
is fully functional.
16
Figure 6. FETG/Modulation and Bias Timing (Fault Condition Detected)
POA
CC
V
V
Yes
Yes
Yes
CC
POA
is below V
. Figure 7 shows the sequence of events as the
____________________________________________________________________
>
POA
TX-D
CC
0
0
1
, the device immediately resumes normal
DETECTION OF
is above V
POA
FETG FAULT
NONMASKED
FETG ALARM
*FETG DIR = 0
V
. When V
TX-D
FETG*
I
MOD
BIAS
CC
0
1
X
is below the V
POD
CC
, the I
rises above V
FETG DIR
FETG DIR
FETG DIR
FETG
2
C interface can be
t
t
t
OFF
OFF
FETG:ON
POA
CC
level. This is
POA
MOD AND
OUTPUTS
Disabled
Disabled
Enabled
BIAS
POD
exceeds
, RDYB
, the
For all device addresses sourced from EEPROM (Table
02h, Register 8Ch), the default device address is A2h
until V
be recalled from the EEPROM.
POA holds the DS1865 in reset until V
level (V
with its ADC and compare analog signals with its quick-
trip monitors. Because V
ADC when V
V
sion greater than the customer-programmable V
ADC limit. This prevents the TX-F and FETG outputs
from glitching during a slow power-up. The TX-F and
FETG outputs do not latch until there is a conversion
above V
The POA alarm is nonmaskable. The TX-F and FETG
outputs are asserted when V
Low-Voltage Operation section for more information.
The DAC1 output has a 0 to 2.5V range, 8 bits of resolu-
tion, and is programmed through the I
DAC1 setting is nonvolatile and password 2 (PW2) pro-
tected.
The M4DAC output has a 0 to 2.5V range, 8 bits of res-
olution, and is controlled by an LUT indexed by the
MON4 voltage. The M4DAC LUT (Table 06h) is non-
volatile and PW2 protected. See the Memory
Organization section for details.
CC
t
FETG:OFF
low alarm, which is cleared by a V
t
t
ON
ON
CC
CC
CC
exceeds V
> V
low limit.
CC
POA
is less than V
) for the part to accurately measure
POA
CC
allowing the device address to
Power-On Analog (POA)
cannot be measured by the
CC
POA
is below V
, POA also asserts the
M4DAC Output
CC
2
DAC1 Output
CC
C interface. The
is at a suitable
ADC conver-
POA
. See the
CC
low