DS1865T+ Maxim Integrated Products, DS1865T+ Datasheet - Page 18

• Manufacturer Part Number: DS1865T+
• Description: IC PON TRIPLEXER CTRLR 28TQFN-EP
• Manufacturer: Maxim Integrated Products

Specifications of DS1865T+

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 28-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PON Triplexer Control and
Monitoring Circuit
See the register map tables for a more complete detail
of each byte’s function, as well as for read/write permis-
sions for each byte.
In addition to volatile memory (SRAM) and nonvolatile
memory (EEPROM), the DS1865 also features shadowed
18
Figure 8. Memory Map
Table 06h contains a MON4-indexed LUT for con-
trol of the M4DAC voltage. The M4DAC LUT has 32
entries that are configurable to act as one 32-entry
LUT or two 16-entry LUTs. When configured as one
32-byte LUT, each entry corresponds to an incre-
ment of 1/32 of the full scale. When configured as
two 16-byte LUTs, the first 16 bytes and the last 16
bytes each correspond to 1/16 of full scale. Either
of the two sections is selected with a separate con-
figuration bit. This LUT is protected by a PW2 level
access.
Auxiliary Memory is EEPROM accessible at the
I
2
C slave address, A0h.
____________________________________________________________________
DEC
127
128
255
0
HEX
7F
80
FF
0
80h
F8h
00h
I
AUXILLARY MEMORY
2
C SLAVE ADDRESS A0h
PW1 LEVEL ACCESS
TABLE 01h
(120 BYTES)
EEPROM
EEPROM
ATB
7Fh
F7h
FFh
80h
C8h
F8h
Shadowed EEPROM
CONFIGURATION AND
MISC. CONTROL
TABLE 02h
NO MEMORY
CONTROL
BITS
C7h
F7h
FFh
I
2
C SLAVE ADDRESS A2h (DEFAULT)
80h
00h
TABLE SELECT BYTE
PASSWORD ENTRY (PWE)
DIGITAL DIAGNOSTIC
PW2 LEVEL ACCESS
LOWER MEMORY
TABLE 03h
(128 BYTES)
FUNCTIONS
(4 BYTES)
EEPROM
7Fh
FFh
EEPROM. Shadowed EEPROM (SEE) can be configured
as either volatile or nonvolatile memory using the SEEB
bit in Table 02h, Register 80h.
The DS1865 uses shadowed EEPROM memory for key
memory addresses that can be rewritten many times. By
default the shadowed EEPROM bit, SEEB, is not set and
these locations act as ordinary EEPROM. By setting
SEEB, these locations function like SRAM cells, which
allow an infinite number of write cycles without concern
of wearing out the EEPROM. This also eliminates the
requirement for the EEPROM write time, t
changes made with SEEB enabled do not affect the
EEPROM, these changes are not retained through
power cycles. The power-up value is the last value writ-
ten with SEEB disabled. This function can be used to
limit the number of EEPROM writes during calibration or
to change the monitor thresholds periodically during nor-
mal operation, helping to reduce the number of times
EEPROM is written. The Memory Organization descrip-
tion indicates which locations are shadowed EEPROM.
80h
MODULATION LUT
TABLE 04h
C7h
80h
TABLE 05h
APC LUT
A7h
80h
TABLE 06h
M4DAC LUT
WR
. Because
9Fh