KS8993F Micrel Inc, KS8993F Datasheet - Page 36

• Manufacturer Part Number: KS8993F
• Description: IC CONV MED 10/100 3PORT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KS8993F

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.89/3.465V
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: KS8993F-EVAL - EVAL KIT EXPERIMENTAL KS8993F
• Lead Free Status / RoHS Status: Not Compliant, Lead free / RoHS Compliant

The SNI interface is a bit wide data interface and therefore runs at the network bit rate (not encoded). An additional
signal on the transmit side indicates when data is valid. Similarly, the receive side has an indicator that conveys when
the data is valid.
For half duplex operation, the KS8993F SCOL signal is used to indicate that a collision has occurred during
transmission.
2.7
The KS8993F supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input / Output
(MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the KS8993F. An
external device with MDC/MDIO capability can be used to read the PHY status or configure the PHY settings. Further
details on the MIIM interface can be found in section 22.2.4.5 of the IEEE 802.3 specification.
The MIIM interface consists of the following:
The following table depicts the MII Management Interface frame format.
For the KS8993F, MIIM register access is selected when bit 2 of the PHY address is set to ‘0’. PHY address bits [4:3]
are not defined for MIIM register access, and hence can be set to either 0’s or 1’s in read/write operation.
2.8
Micrel, Inc.
June 2009
MII Management Interface (MIIM)
Serial Management Interface (SMI)
Read
Write
A physical connection that incorporates the data line (MDIO) and the clock line (MDC).
A specific protocol that operates across the aforementioned physical connection that allows an external
controller to communicate with the KS8993F device.
Access to a set of six 16-bits registers, consisting of standard MIIM registers [0:5].
Preamble
32 1’s
32 1’s
Transmit enable
Serial transmit data
Transmit clock
Collision detection
Carrier sense
Serial receive data
Receive clock
Start of
Frame
01
01
Table 5: MII Management Interface frame format
Read/Write
OP Code
10
01
TXEN
TXD
TXC
COL
CRS
RXD
RXC
Bits [4:0]
Address
xx0AA
xx0AA
PHY
36
Bits [4:0]
Address
RRRRR
RRRRR
REG
SMTXEN
SMTXD[0]
SMTXC
SCOL
SMRXDV
SMRXD[0]
SMRXC
TA
Z0
10
DDDDDDDD_DDDDDDDD
DDDDDDDD_DDDDDDDD
[e-mail]
Bits [15:0]
Data
or [phone]
M9999-062509
KS8993F/FL
Idle
Z
Z