KS8993F Micrel Inc, KS8993F Datasheet - Page 51

• Manufacturer Part Number: KS8993F
• Description: IC CONV MED 10/100 3PORT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KS8993F

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.89/3.465V
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: KS8993F-EVAL - EVAL KIT EXPERIMENTAL KS8993F
• Lead Free Status / RoHS Status: Not Compliant, Lead free / RoHS Compliant

Advanced Control Registers
4.1
Register 0 (0x00): Chip ID0
Register 1 (0x01): Chip ID1 / Start Switch
Register 2 (0x02): Global Control 0
Micrel, Inc.
Bit
7-0
Bit
7-4
3-1
0
Bit
7
6-4
June 2009
(Decimal)
Register
104-109
110-111
112-120
121-122
123-124
125-126
96-103
127
92
93
94
95
Global Registers
Name
Family ID
Name
Chip ID
Revision ID
Start Switch
Name
New Back-off
Enable
802.1p base
priority
0x60-0x67
0x68-0x6D
0x6E-0x6F
0x70-0x78
0x79-0x7A
0x7B-0x7C
0x7D-0x7E
0x7F
Register
(Hex)
0x5C
0x5D
0x5E
0x5F
R/W
RO
R/W
RO
RO
RW
R/W
R/W
R/W
LNK Partner Vendor Info (3)
LNK Partner Model Info (1)
LNK Partner Model Info (2)
LNK Partner Model Info (3)
TOS Priority Control Registers
Switch Engine’s MAC Address Registers
Indirect Access Control Registers
Indirect Data Registers
Digital Testing Status Registers
Digital Testing Control Registers
Analog Testing Control Registers
Analog Testing Status Register
Description
Chip family
Description
0x0 is assigned to F series. (93F)
Revision ID
= 1, start the chip when external pins
Note: In (PS1, PS0) = (0, 0) mode, the chip will start automatically after
= 0, chip will not start when external pins (PS1, PS0) = (0,1),
Description
New back-off algorithm designed for UNH
Used to classify priority for incoming 802.1Q packets. “user
priority” is compared against this value.
1 = Enable
0 = Disable
(1,0), or (1,1)
(PS1, PS0) = (0,1), (1,0), or (1,1)
trying to read the external EEPROM. If EEPROM does not
exists, the chip will use pin strapping and default values for all
internal registers. If EEPROM is present, the contents in the
EEPROM will be checked. The switch will check: (1) Register 0
= 0x93, (2) Register 1 bits [7:4] = 0x0. If this check is OK, the
contents in the EEPROM will override chip register default
values.
51
Description
[e-mail]
or [phone]
M9999-062509
Default
0x93
Default
0x0
-
-
Default
0x0
0x4
KS8993F/FL