TC58V64BDC Toshiba, TC58V64BDC Datasheet - Page 30

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TC58V64BDC

Manufacturer Part Number
TC58V64BDC
Description
IC 64MBIT NAND FLASH 3V 44-TSOP
Manufacturer
Toshiba
Datasheet

Specifications of TC58V64BDC

Memory Size
8MB
Memory Type
EEPROM - Smart Media
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
(11)
(12)
RY
/
WE
RE
I/O
BY
Several programming cycles on the same page (Partial Page Program)
Note regarding the RE signal
mode. Therefore, once the device has been set to Read mode by a “00H”, “01H” or “50H” command, the
internal column address counter is incremented by the RE clock independently of the address input timing,
If the RE clock input pulses start before the address input, and the pointer reaches the last column
address, an internal read operation (array to register) will occur and the device will enter Busy state. (Refer
to Figure 25.)
2nd programming
5th programming
1st programming
A page can be divided into up to 5 segments. Each segment can be programmed individually as follows:
Hence the RE clock input must start after the address input.
RE The internal column address counter is incremented synchronously with the RE clock in Read
00H/01H/50H
Result
Note: The input data for unprogrammed or previously programmed page segments must be “1”
(i.e. the inputs for all page bytes outside the segment which is to be programmed should be set to all “1”).
Data Pattern 1
Data Pattern 1
All 1s
Data Pattern 2
Data Pattern 2
All 1s
Figure 24.
Figure 25.
All 1s
Address input
All 1s
Data Pattern 5
Data Pattern 5
2001-10-24 30/33
TC58V64BDC

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