MT16LSDF6464HG-133D2 Micron Technology Inc, MT16LSDF6464HG-133D2 Datasheet - Page 7

• Manufacturer Part Number: MT16LSDF6464HG-133D2
• Description: MODULE SDRAM 512MB 144SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16LSDF6464HG-133D2

• Memory Type: SDRAM
• Memory Size: 512MB
• Speed: 133MHz
• Package / Case: 144-SODIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 144SODIMM
• Device Core Size: 64b
• Organization: 64Mx64
• Total Density: 512MByte
• Chip Density: 256Mb
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 1.096A
• Number Of Elements: 16
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 144
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CAS Latency
tween the registration of a READ command and the
availability of the first piece of output data. The la-
tency can be set to two or three clocks.
and the latency is m clocks, the data will be available by
clock edge n + m. The DQs will start driving as a result of
the clock edge one cycle earlier (n + m - 1), and provided
that the relevant access times are met, the data will be
valid by clock edge n + m. For example, assuming that
the clock cycle time is such that all relevant access times
are met, if a READ command is registered at T0 and the
latency is programmed to two clocks, the DQs will start
driving after T1 and the data will be valid by T2, as
shown in Figure 1. Table 1 indicates the operating fre-
quencies at which each CAS latency setting can be used.
operation or incompatibility with future versions
may result.
32/64 Meg x 64 SDRAM SODIMM
SD16C32_64x64HG_A.pm6; Rev. A, Pub 7/01
COMMAND
COMMAND
The CAS latency is the delay, in clock cycles, be-
If a READ command is registered at clock edge n,
Reserved states should not be used as unknown
CLK
CLK
DQ
DQ
READ
READ
T0
T0
CAS Latency = 2
CAS Latency
Figure 1
NOP
NOP
T1
T1
t
t AC
LZ
CAS Latency = 3
T2
T2
NOP
NOP
t
t AC
LZ
D
t OH
OUT
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
T4
7
Operating Mode
M7 and M8 to zero; the other combinations of values for
M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.
because unknown operation or incompatibility with
future versions may result.
Write Burst Mode
M0-M2 applies to both READ and WRITE bursts; when
M9 = 1, the programmed burst length applies to
READ bursts, but write accesses are single-location
(nonburst) accesses.
SPEED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
-13E
-133
-10E
The normal operating mode is selected by setting
Test modes and reserved states should not be used
When M9 = 0, the burst length programmed via
LATENCY = 2
ALLOWABLE OPERATING
≤ 133
≤ 100
≤ 100
CAS
CAS Latency
FREQUENCY (MHz)
Table 1
SDRAM SODIMM
256/512MB (x64)
LATENCY = 3
PRELIMINARY
©2001, Micron Technology, Inc.
≤ 143
≤ 133
≤ 125
CAS