MT16LSDF6464HG-133D2 Micron Technology Inc, MT16LSDF6464HG-133D2 Datasheet - Page 9

• Manufacturer Part Number: MT16LSDF6464HG-133D2
• Description: MODULE SDRAM 512MB 144SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16LSDF6464HG-133D2

• Memory Type: SDRAM
• Memory Size: 512MB
• Speed: 133MHz
• Package / Case: 144-SODIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 144SODIMM
• Device Core Size: 64b
• Organization: 64Mx64
• Total Density: 512MByte
• Chip Density: 256Mb
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 1.096A
• Number Of Elements: 16
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 144
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TRUTH TABLE – SDRAM COMMANDS AND DQMB OPERATION
(Note: 1)
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
COMMANDS
ence of available commands. For a more detailed descrip-
32/64 Meg x 64 SDRAM SODIMM
SD16C32_64x64HG_A.pm6; Rev. A, Pub 7/01
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
The following Truth Table provides a general refer-
2. A0-A11 (256MB), A0-A12 (512MB) define the op-code written to the Mode Register, and should be driven low.
3. A0-A11 (256MB), A0-A12 (512MB) provide device row address. BA0, BA1 determine which device bank is made active.
4. A0-A8 provide device column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW
5. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: both device banks are precharged and
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
disables the auto precharge feature; BA0, BA1 determine which device bank is being read from or written to.
BA0, BA1 are “Don’t Care.”
9
CS# RAS# CAS# WE# DQMB ADDR
H
L
L
L
L
L
L
L
–
–
L
tion of commands and operations, refer to the 128Mb and
the 256Mb SDRAM component data sheet.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
H
H
H
X
L
L
L
L
–
–
H
H
H
H
X
L
L
L
–
–
L
H
X
H
H
H
L
L
L
L
–
–
L/H
L/H
H
X
X
X
X
X
X
X
L
SDRAM SODIMM
8
8
256/512MB (x64)
Bank/Row
Op-Code
Bank/Col
Bank/Col
Code
X
X
X
X
–
–
PRELIMINARY
©2001, Micron Technology, Inc.
High-Z
Active
Active
DQs NOTES
Valid
X
X
X
X
X
X
X
6, 7
3
4
4
5
2
8
8