MT8HTF3264AY-53EB3 Micron Technology Inc, MT8HTF3264AY-53EB3 Datasheet - Page 12
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MT8HTF3264AY-53EB3
Manufacturer Part Number
MT8HTF3264AY-53EB3
Description
MODULE DDR2 SDRAM 256MB 240-DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT8HTF3264AY-53EB3.pdf
(18 pages)
Specifications of MT8HTF3264AY-53EB3
Memory Type
DDR2 SDRAM
Memory Size
256MB
Speed
267MHz
Package / Case
240-DIMM
Main Category
DRAM Module
Sub-category
DDR2 SDRAM
Module Type
240UDIMM
Device Core Size
64b
Organization
32Mx64
Total Density
256MByte
Chip Density
256Mb
Maximum Clock Rate
533MHz
Operating Supply Voltage (typ)
1.8V
Operating Current
1.28A
Number Of Elements
8
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
240
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1144
I
Table 10: DDR2 I
Values shown for MT47H32M8 DDR2 SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8)
component data sheet
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
Parameter
Operating one bank active-precharge current:
(I
mands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
4, CL = CL (I
t
dress bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
CKE is LOW; Other control and address bus inputs are stable; Data bus in-
puts are floating
Precharge quiet standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
Active power-down current: All device banks open;
t
are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
mands; Other control and address bus inputs are switching; Data bus inputs
are switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
t
bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
read, I
MAX (I
Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:
(I
trol and address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and ad-
dress bus inputs are floating; Data bus inputs are floating
DD
RCD =
CK (I
RAS MAX (I
RP =
DD
DD
),
) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
DD
Specifications
t
t
RAS =
RP (I
OUT
DD
t
); CKE is LOW; Other control and address bus inputs
RCD (I
),
= 0mA; BL = 4, CL = CL (I
DD
t
DD
RP =
DD
t
); CKE is HIGH, S# is HIGH between valid commands; Address
RAS MIN (I
), AL = 0;
DD
),
); CKE is HIGH, S# is HIGH between valid commands; Ad-
t
t
RP =
RP (I
DD
DD
t
RP (I
Specifications and Conditions – 256MB
t
DD
DD
CK =
t
); CKE is HIGH, S# is HIGH between valid commands;
CK =
), AL = 0;
); CKE is HIGH, S# is HIGH between valid com-
DD
t
); CKE is HIGH, S# is HIGH between valid com-
CK (I
t
CK (I
DD
DD
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
DD
t
CK =
),
), AL = 0;
); REFRESH command at every
t
RC =
t
CK (I
t
RC (I
t
DD
CK =
),
DD
t
CK =
t
t
RAS =
CK =
),
t
t
CK (I
CK =
t
RAS =
t
DD4W
CK =
t
CK (I
t
DD
CK (I
t
OUT
t
CK =
t
RAS MAX (I
t
CK (I
CK =
),
12
t
DD
RAS MIN (I
t
= 0mA; BL =
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
DD
RAS =
),
t
DD
CK (I
),
t
t
CK (I
); CKE is
RAS =
t
RC =
t
RFC
t
DD
RAS
DD
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
);
t
DD
),
);
RC
),
Symbol
I
I
I
I
I
I
I
I
DD3PF
DD3PS
DD4W
DD2Q
I
I
DD2N
DD3N
DD4R
I
I
DD2P
DD0
DD1
DD5
DD6
-667
1520
1440
1440
720
800
320
320
240
400
40
48
40
© 2003 Micron Technology, Inc. All rights reserved.
I
DD
1280
1200
1360
-53E
640
720
280
280
200
320
40
48
40
Specifications
-40E
1000
1320
600
680
200
240
160
240
920
40
48
40
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA