MT8HTF3264AY-53EB3 Micron Technology Inc, MT8HTF3264AY-53EB3 Datasheet - Page 14
![MODULE DDR2 SDRAM 256MB 240-DIMM](/photos/7/83/78383/mfg557-240-dimm_sml.jpg)
MT8HTF3264AY-53EB3
Manufacturer Part Number
MT8HTF3264AY-53EB3
Description
MODULE DDR2 SDRAM 256MB 240-DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT8HTF3264AY-53EB3.pdf
(18 pages)
Specifications of MT8HTF3264AY-53EB3
Memory Type
DDR2 SDRAM
Memory Size
256MB
Speed
267MHz
Package / Case
240-DIMM
Main Category
DRAM Module
Sub-category
DDR2 SDRAM
Module Type
240UDIMM
Device Core Size
64b
Organization
32Mx64
Total Density
256MByte
Chip Density
256Mb
Maximum Clock Rate
533MHz
Operating Supply Voltage (typ)
1.8V
Operating Current
1.28A
Number Of Elements
8
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
240
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1144
Table 11: DDR2 I
Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8)
component data sheet
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
Parameter
Operating one bank active-precharge current:
t
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
4, CL = CL (I
(I
Address bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
CKE is LOW; Other control and address bus inputs are stable; Data bus in-
puts are floating
Precharge quiet standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Da-
ta bus inputs are switching
Active power-down current: All device banks open;
=
puts are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
mands; Other control and address bus inputs are switching; Data bus
inputs are switching
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (I
(I
Address bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
read, I
MAX (I
mands; Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:
(I
trol and address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
RC (I
RAS MAX (I
DD
DD
DD
t
CK (I
),
),
) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
DD
t
t
RCD =
RP =
OUT
DD
DD
),
),
t
); CKE is LOW; Other control and address bus in-
RAS =
= 0mA; BL = 4, CL = CL (I
t
t
DD
RP (I
RP =
DD
t
RCD (I
), AL = 0;
),
t
DD
t
t
RP =
RAS MIN (I
RP (I
); CKE is HIGH, S# is HIGH between valid commands;
DD
DD
DD
); CKE is HIGH, S# is HIGH between valid commands;
t
RP (I
Specifications and Conditions – 512MB
t
CK =
t
); CKE is HIGH, S# is HIGH between valid com-
CK =
DD
DD
t
); CKE is HIGH, S# is HIGH between valid com-
DD
CK (I
t
); CKE is HIGH, S# is HIGH between valid
CK (I
), AL = 0;
DD
DD
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
DD
),
), AL = 0;
); REFRESH command at every
t
RC =
t
CK =
t
RC (I
t
CK =
t
CK (I
DD
t
CK =
t
CK =
),
t
t
DD
CK (I
CK =
t
RAS =
),
t
CK
t
CK (I
t
t
RAS =
DD
CK (I
t
OUT
CK =
t
DD4W
t
CK (I
CK =
),
14
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
DD
RAS MIN
t
= 0mA; BL =
DD
RAS =
),
t
DD
t
CK (I
RAS MAX
),
t
t
CK (I
); CKE is
RAS =
t
RC =
t
RFC
t
DD
RAS
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
);
);
Symbol
I
I
I
I
I
I
I
I
DD3PF
DD3PS
DD4W
I
I
DD2Q
DD2N
DD3N
I
I
DD2P
DD4R
DD0
DD1
DD5
DD6
1560
1640
1840
-80E
-800
800
920
400
400
320
560
56
96
56
1360
1440
1440
-667
720
840
360
400
280
520
© 2003 Micron Technology, Inc. All rights reserved.
56
96
56
I
DD
1120
1160
1360
-53E
Specifications
640
760
320
360
240
440
56
96
56
-40E
1320
640
720
280
320
200
360
920
920
56
96
56
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA