MT8HTF3264AY-53EB3 Micron Technology Inc, MT8HTF3264AY-53EB3 Datasheet - Page 16
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MT8HTF3264AY-53EB3
Manufacturer Part Number
MT8HTF3264AY-53EB3
Description
MODULE DDR2 SDRAM 256MB 240-DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT8HTF3264AY-53EB3.pdf
(18 pages)
Specifications of MT8HTF3264AY-53EB3
Memory Type
DDR2 SDRAM
Memory Size
256MB
Speed
267MHz
Package / Case
240-DIMM
Main Category
DRAM Module
Sub-category
DDR2 SDRAM
Module Type
240UDIMM
Device Core Size
64b
Organization
32Mx64
Total Density
256MByte
Chip Density
256Mb
Maximum Clock Rate
533MHz
Operating Supply Voltage (typ)
1.8V
Operating Current
1.28A
Number Of Elements
8
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
240
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1144
Table 12: DDR2 I
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
Parameter
Operating one bank active-precharge current:
(I
Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
= CL (I
t
puts are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
LOW; Other control and address bus inputs are stable; Data bus inputs are float-
ing
Precharge quiet standby current: All device banks idle;
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
Active power-down current: All device banks open;
t
stable; Data bus inputs are floating
Active standby current: All device banks open;
MAX (I
Other control and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
t
are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst read,
I
t
inputs are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and ad-
dress bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads; I
(I
HIGH between valid commands; Address bus inputs are stable during deselects;
Data bus inputs are switching
RCD (I
CK (I
RP (I
OUT
RP =
DD
DD
),
),
= 0mA; BL = 4, CL = CL (I
DD
DD
t
t
t
RAS =
DD
RP (I
RC =
DD
DD
OUT
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
); CKE is LOW; Other control and address bus inputs are
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands; Address bus in-
),
DD
= 0mA; BL = 4, CL = CL (I
t
t
RP =
RC (I
t
); CKE is HIGH, S# is HIGH between valid commands; Address bus
RAS MIN (I
DD
t
RP (I
t
CK =
),
DD
t
RRD =
DD
Specifications and Conditions – 1GB
DD
DD
t
t
); CKE is HIGH, S# is HIGH between valid commands;
CK (I
CK =
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands;
t
RRD (I
DD
DD
t
CK (I
), AL = 0;
),
t
RC =
DD
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
DD
DD
t
CK =
),
); REFRESH command at every
), AL =
t
t
RCD =
RC (I
t
CK =
t
CK (I
DD4W
DD
t
RCD (I
t
t
),
DD
RCD (I
CK (I
t
),
RAS =
t
CK =
t
t
DD
RAS =
CK =
DD
t
DD
CK =
) - 1 ×
),
t
); CKE is HIGH, S# is
t
CK =
t
t
RAS MIN (I
CK (I
RAS =
t
CK (I
t
OUT
t
CK =
t
RAS MAX (I
t
CK (I
CK =
16
t
CK (I
DD
= 0mA; BL = 4, CL
DD
t
),
t
DD
RAS MAX (I
CK (I
),
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
t
DD
CK (I
); CKE is
RAS =
t
DD
RC =
);
t
RFC (I
DD
),
t
DD
DD
CK =
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
); CKE is
RCD =
t
t
),
); CKE
RC
RAS
DD
t
RP =
DD
t
CK
)
),
Symbol
I
I
I
I
I
I
I
I
DD3PF
DD3PS
DD4W
DD2Q
I
I
DD2N
DD3N
DD4R
I
I
I
DD2P
DD0
DD1
DD5
DD6
DD7
-667
1280
1280
2080
2400
720
800
440
480
320
560
56
80
56
© 2003 Micron Technology, Inc. All rights reserved.
I
DD
-53E
1040
1160
2000
2320
640
760
328
360
240
440
56
80
56
Specifications
1760
2080
-40E
560
640
280
320
200
360
880
880
56
80
56
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA