MT18VDDF12872DY-40BD3 Micron Technology Inc, MT18VDDF12872DY-40BD3 Datasheet - Page 15

• Manufacturer Part Number: MT18VDDF12872DY-40BD3
• Description: MODULE DDR 1GB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDF12872DY-40BD3

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 512Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Current: 1.8A
• Number Of Elements: 18
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 12: IDD Specifications and Conditions – 512MB
DDR SDRAM components only
Notes: 1–5, 8, 10, 12, 48; notes appear on pages 21–24; 0°C
pdf: 09005aef8074e85b, source: 09005aef8072fe49
DDF18C64_128x72G.fm - Rev. C 11/04 EN
PARAMETER/CONDITION
OPERATING CURRENT: One device bank; Active-Precharge;
t
once per clock cyle; Address and control inputs changing once
every two clock cycles
OPERATING CURRENT: One device bank; Active -Read Precharge;
Burst = 4;
control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks
idle; Power-down mode;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
t
once per clock cycle. V
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active;
Power-down mode;
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
bank; Active-Precharge;
t
cycle; Address and other control inputs changing once per clock
cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank
active; Address and control inputs changing once per clock cycle;
t
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once per
clock cycle;
twice per clock cycle
AUTO REFRESH CURRENT
SELF REFRESH CURRENT: CKE
OPERATING CURRENT: Four device bank interleaving READs (BL = 4)
with auto precharge,
control inputs change only during Active READ, or WRITE
commands
RC =
CK MIN; CKE = HIGH; Address and other control inputs changing
CK =
CK =
t
t
t
RC (MIN);
CK (MIN); DQ, DM, and DQS inputs changing twice per clock
CK (MIN); I
t
RC =
t
CK =
t
RC (MIN);
t
CK =
OUT
t
CK (MIN); DQ, DM, and DQS inputs changing
t
CK =
= 0mA
t
t
IN
RC =
CK (MIN); DQ, DM and DQS inputs changing
t
t
= V
RC =
CK =
t
t
CK (MIN); CKE = LOW
CK =
t
REF
RC (MIN);
t
t
RAS (MAX);
CK (MIN); CKE = (LOW)
0.2V
for DQ, DQS, and DM
t
CK (MIN); I
t
CK =
OUT
t
CK (MIN); Address and
t
t
REFC =
REFC = 7.8125µs
= 0mA; Address and
t
RFC (MIN)
t
15
CK =
T
A
+70°C; V
SYMBOL
Micron Technology, Inc., reserves the right to change products or specifications without notice.
I
I
I
I
I
I
I
I
DD4W
I
184-PIN DDR SDRAM RDIMM
I
DD3N
DD4R
DD5A
I
I
DD2P
DD2F
DD3P
DD
DD
DD1
DD6
DD7
DD
5
0
512MB, 1GB (x72, ECC, SR)
= V
DD
2,250
3,060
1,080
3,150
3,150
4,590
7,380
-335
900
540
108
72
72
Q = +2.5V ±0.2V
MAX
2,250
2,880
2,700
2,700
4,230
6,300
-262
810
450
900
108
72
72
©2004 Micron Technology, Inc. All rights reserved.
-265/-
-26A/
2,160
2,610
2,700
2,700
4,230
6,300
202
810
450
900
108
72
72
UNITS NOTES
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
21, 28,
21, 28,
20, 43
20, 43
20, 43
20, 45
24, 45
20, 44
45
46
45
42
20
9