MT18VDDF12872DY-40BD3 Micron Technology Inc, MT18VDDF12872DY-40BD3 Datasheet - Page 19

• Manufacturer Part Number: MT18VDDF12872DY-40BD3
• Description: MODULE DDR 1GB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDF12872DY-40BD3

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 512Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Current: 1.8A
• Number Of Elements: 18
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC
Notes: 1–5, 12-15, 29, 49; notes appear on pages 21–24; 0°C
pdf: 09005aef8074e85b, source: 09005aef8072fe49
DDF18C64_128x72G.fm - Rev. C 11/04 EN
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command delay
Data valid output window
Operating Conditions (-26A, -265, -202)
CL = 2.5
CL = 2
19
SYMBOL
t
T
t
t
CK (2.5)
t
t
t
t
DQSCK
WPRES
t
A
t
t
t
t
t
t
t
CK (2)
DQSH
DQSQ
WPRE
DIPW
t
t
t
t
WPST
DQSL
DQSS
t
t
t
t
t
RPRE
MRD
RPST
t
WTR
t
t
t
t
DSH
t
t
t
t
QHS
RAP
RCD
RRD
t
IPW
RAS
t
t
t
DSS
t
t
t
RFC
WR
DH
QH
na
AC
CH
HP
HZ
IH
IH
CL
DS
RC
RP
LZ
IS
IS
+70°C; V
F
S
F
S
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM RDIMM
7.5/10
t
-0.75
-0.75
-0.75
t
MIN
0.45
0.45
1.75
0.35
0.35
0.75
0.90
0.90
0.25
QHS
HP -
2.2
0.9
0.4
t
7.5
0.5
0.5
0.2
0.2
0.4
15
40
20
65
75
20
20
15
15
QH -
DD
1
1
0
1
-26A/-265
512MB, 1GB (x72, ECC, SR)
t
CH,
= V
t
120,000
DQSQ
t
DD
MAX
+0.75
+0.75
+0.75
CL
0.55
0.55
1.25
0.75
0.5
1.1
0.6
0.6
13
13
Q = +2.5V ±0.2V
t
t
MIN
0.45
0.45
0.35
0.35
0.75
0.25
-0.8
-0.8
-0.8
QHS
t
HP -
0.6
0.6
0.2
0.2
1.1
1.1
1.1
1.1
2.2
0.9
0.4
0.4
10
16
40
20
70
80
20
20
15
15
QH -
8
2
0
1
t
CH,
-202
©2004 Micron Technology, Inc. All rights reserved.
120,000
t
DQSQ
MAX
t
+0.8
0.55
0.55
+0.8
1.25
+0.8
CL
0.6
1.1
0.6
0.6
13
13
1
UNITS
t
t
t
t
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
NOTES
40, 46
40, 46
23, 27
23, 27
22, 23
16, 37
16, 37
22, 23
31, 49
18, 19
26
26
27
30
12
12
12
12
44
38
38
17
22