MT5VDDT1672HG-26AC3 Micron Technology Inc, MT5VDDT1672HG-26AC3 Datasheet - Page 11
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MT5VDDT1672HG-26AC3
Manufacturer Part Number
MT5VDDT1672HG-26AC3
Description
MODULE SDRAM DDR 128MB 200SODIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT5VDDT1672HY-335K1.pdf
(16 pages)
Specifications of MT5VDDT1672HG-26AC3
Memory Type
DDR SDRAM
Memory Size
128MB
Speed
266MT/s
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
200SODIMM
Device Core Size
72b
Organization
16Mx72
Total Density
128MByte
Access Time (max)
75ps
Maximum Clock Rate
266MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
925mA
Number Of Elements
5
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Serial Presence-Detect
Table 11:
Table 12:
PDF: 09005aef80a8e793/Source: 09005aef80a8e767
dd5c16_32x72h.fm - Rev. F 2/07 EN
Parameter/Condition
Parameter/Condition
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: I
Input leakage current: V
Output leakage current: V
Standby current: SCL = SDA = V
Power supply current: SCL clock frequency = 100 kHz
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to V
Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
Notes:
OUT
IN
= 3mA
OUT
= GND to V
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
= GND to V
the falling or rising edge of SDA.
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tance, and the EEPROM does not respond to its slave address.
DD
- 0.3V; All other inputs = V
DD
SS
SS
DD
; V
; V
DDSPD
DDSPD
128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM
= +2.3V to +3.6V
= +2.3V to +3.6V
11
SS
or V
DD
t
WRC) is the time from a valid stop condition of a write
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol
t
t
t
t
t
HD:DAT
HD:STA
SU:DAT
SU:STO
SU:STA
t
t
t
t
HIGH
LOW
f
WRC
t
t
BUF
SCL
Symbol
AA
DH
t
t
V
t
R
F
I
DDSPD
V
V
V
I
I
I
I
LO
SB
CC
OL
LI
IH
IL
V
Min
DDSPD
200
100
0.2
1.3
0.6
0.6
1.3
0.6
0.6
–
0
–
–
–
–
Min
2.3
–1
Serial Presence-Detect
–
–
–
–
–
× 0.7
Max
©2004 Micron Technology, Inc. All rights reserved.
300
400
0.9
0.3
50
10
–
–
–
–
–
–
–
–
–
V
V
DDSPD
DDSPD
Units
kHz
ms
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
Max
3.6
0.4
10
10
30
2
+ 0.5
× 0.3
Notes
Units
1
2
2
3
4
mA
µA
µA
µA
V
V
V
V