MT5VDDT1672HG-26AC3 Micron Technology Inc, MT5VDDT1672HG-26AC3 Datasheet - Page 9

• Manufacturer Part Number: MT5VDDT1672HG-26AC3
• Description: MODULE SDRAM DDR 128MB 200SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT5VDDT1672HG-26AC3

• Memory Type: DDR SDRAM
• Memory Size: 128MB
• Speed: 266MT/s
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 72b
• Organization: 16Mx72
• Total Density: 128MByte
• Access Time (max): 75ps
• Maximum Clock Rate: 266MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 925mA
• Number Of Elements: 5
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

I
Table 9:
PDF: 09005aef80a8e793/Source: 09005aef80a8e767
dd5c16_32x72h.fm - Rev. F 2/07 EN
Parameter/Condition
Operating one bank active-precharge current:
t
per clock cycle; Address and control inputs changing once every two clock
cycles
Operating one bank active-read-precharge current: Burst = 4;
t
I
Precharge power-down standby current: All device banks idle; Power-
down mode;
Idle standby current: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock
cycle; V
Active power-down standby current: One device bank active; Power-
down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank;
Active-precharge;
inputs changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
Operating current: Burst = 2; Reads; Continuous burst; One device bank
active; Address and control inputs changing once per clock cycle;
t
Operating current: Burst = 2; Writes; Continuous burst; One device bank
active; Address and control inputs changing once per clock cycle;
t
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating current: Four device bank interleaving READs (BL = 4) with
auto precharge;
inputs change only during active READ or WRITE commands
DD
OUT
RC =
RC =
CK =
CK =
Specifications
= 0mA; Address and control inputs changing once per clock cycle
t
t
t
t
RC (MIN);
RC (MIN);
CK (MIN); I
CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
IN
= V
REF
t
t
DDR I
Values shown for MT46V16M16 DDR SDRAM only and are computed from values specified in the
256Mb (16 Meg x 16) component data sheet
CK =
CK =
t
for DQ, DQS, and DM
t
t
CK =
CK =
RC =
OUT
t
RC =
t
t
CK (MIN); CKE = (LOW)
CK (MIN); CKE = LOW
DD
= 0mA
t
t
t
CK (MIN); DQ, DM, and DQS inputs changing once
CK (MIN);
RC (MIN);
t
Specifications and Conditions – 128MB
RAS (MAX);
t
CK =
t
CK =
t
CK (MIN); Address and control
t
CK (MIN); DQ, DM, and DQS
128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM
t
t
REFC =
REFC = 7.8125µs
t
CK =
9
t
RFC (MIN)
t
CK (MIN);
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol
I
I
I
I
I
I
I
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
DD
4W
3N
5A
2P
3P
4R
2F
0
1
5
6
7
1,100
1,275
2,200
-335
625
900
250
150
300
900
20
30
20
Electrical Specifications
©2004 Micron Technology, Inc. All rights reserved.
1,175
1,900
-262
625
850
225
125
250
925
725
20
30
20
-26A/
1,175
1,900
-265
525
775
225
125
250
925
725
20
30
20
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA