MT16HTF12864AY-53ED4 Micron Technology Inc, MT16HTF12864AY-53ED4 Datasheet - Page 9

• Manufacturer Part Number: MT16HTF12864AY-53ED4
• Description: MODULE DDR2 1GB 240-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16HTF12864AY-53ED4

• Memory Type: DDR2 SDRAM
• Memory Size: 1GB
• Speed: 533MT/s
• Package / Case: 240-DIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240UDIMM
• Device Core Size: 64b
• Organization: 128Mx64
• Total Density: 1GByte
• Chip Density: 512Mb
• Access Time (max): 50ps
• Maximum Clock Rate: 533MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.216A
• Number Of Elements: 16
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 7:
PDF: 09005aef80f09084/Source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
Parameter/Condition
Operating one device bank active-precharge current;
t
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one device bank active-read-precharge current; I
= 4, CL = CL (I
t
inputs are switching; Data pattern is same as I
Precharge power-down current; All device banks idle;
LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge quiet standby current; All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge standby current; All device banks idle;
S# is HIGH; Other control and address bus inputs are switching; Data bus inputs
are switching
Active power-down current; All device banks open;
(I
stable; Data bus inputs are floating
Active standby current; All device banks open;
MAX (I
Other control and address bus inputs are switching; Data bus inputs are
switching
Operating burst write current; All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
t
are switching; Data bus inputs are switching
Operating burst read current; All device banks open; Continuous burst reads,
I
t
inputs are switching; Data bus inputs are switching
Burst refresh current;
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
Operating device bank interleave read current; All device banks
interleaving reads, I
(I
HIGH, S# is HIGH between valid commands; Address bus inputs are stable during
DESELECTs; Data bus inputs are switching; See I
data sheet for detail
RC =
RCD =
RP (I
OUT
RP =
DD
DD
); CKE is LOW; Other control and address bus inputs are
);
= 0mA; BL = 4, CL = CL (I
DD
t
t
t
RP (I
CK =
RC (I
DD
t
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
RCD (I
),
DD
DD
t
t
RP =
CK (I
); CKE is HIGH, S# is HIGH between valid commands; Address bus
),
DD
DD
DDR2 I
Values shown for DDR2 SDRAM components only
t
), AL = 0;
RAS =
); CKE is HIGH, S# is HIGH between valid commands; Address bus
DD
t
RP (I
Notes:
),
OUT
t
DD
RC =
DD
t
RAS MIN (I
DD
= 0mA; BL = 4, CL = CL (I
t
); CKE is HIGH, S# is HIGH between valid commands;
CK =
t
Specifications and Conditions – 512MB
CK =
), AL = 0;
t
RC (I
1. a = Value calculated as one module rank in this operating condition, and all other module
2. b = Value calculated reflects all module ranks in this operating condition.
DD
t
CK (I
t
), AL = 0;
ranks in I
CK (I
DD
DD
),
t
DD
); CKE is HIGH, S# is HIGH between valid
CK =
DD
t
RRD =
); REFRESH command at every
),
DD
t
t
CK =
t
RC =
CK (I
512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
2
t
P
RRD (I
(CKE LOW).
DD
t
t
DD
DD
RC (I
CK (I
DD
4W
),
7 conditions in component
t
CK =
), AL =
DD
t
RAS =
DD
DD
t
CK =
),
t
),
),
CK =
t
t
RCD =
CK (I
t
t
RAS =
RAS =
t
t
t
CK =
t
RCD (I
t
CK (I
RAS MAX (I
CK =
t
CK =
t
CK
9
DD
t
DD
RCD (I
t
t
),
t
CK (I
RAS MIN (I
RAS MAX (I
t
DD
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
CK (I
t
t
OUT
); CKE is HIGH,
CK (I
RAS =
) - 1 ×
t
DD
RFC (I
DD
= 0mA; BL
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
DD
); CKE is
); CKE is
); CKE is
t
),
),
RAS
t
CK
DD
DD
t
RP =
DD
),
)
),
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
DD
DD
DD
I
I
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
2P
3P
4R
0
1
5
6
7
b
b
a
a
a
b
b
a
b
b
b
a
Electrical Specifications
1,560
1,480
2,880
2,040
-667
680
760
560
640
480
800
80
96
80
©2003 Micron Technology, Inc. All rights reserved.
1,320
1,240
2,720
1,960
-53E
680
760
560
560
400
640
80
96
80
1,040
2,640
1,880
-40E
640
720
400
480
320
480
960
80
96
80
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA