ISL8200MIRZ Intersil, ISL8200MIRZ Datasheet - Page 15

• Manufacturer Part Number: ISL8200MIRZ
• Description: IC BUCK SYNC ADJ 10A 23-QFN
• Manufacturer: Intersil
• Type: Point of Load (POL) Non-Isolatedr

Specifications of ISL8200MIRZ

• Output: 0.6 ~ 6V
• Number Of Outputs: 1
• Power (watts): 60W
• Mounting Type: Surface Mount
• Voltage - Input: 3 ~ 20V
• Package / Case: 23-QFN
• 1st Output: 0.6 ~ 6 VDC @ 10A
• Size / Dimension: 0.59" L x 0.59" W x 0.09" H (15mm x 15mm x 2.2mm)
• Power (watts) - Rated: 60W
• Operating Temperature: -40°C ~ 85°C
• Current - Output: 10A
• Voltage - Output: 0.6 ~ 6 V
• Frequency - Switching: 700kHz ~ 1.5MHz
• Synchronous Rectifier: Yes
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• 3rd Output: -
• 2nd Output: -

when recovering from faults. A 1nF capacitor is
recommended as a starting value for typical application.
The voltage on the FF pin needs to be above 0.7V prior to
soft-start and during PWM switching to ensure reliable
regulation. In a typical application, FF pin can be shorted
to EN pin.
Fault Handshake
In a multi-module system, with the EN pins wired OR’ed
together, all modules can immediately turn off, at one
time, when a fault condition occurs in one or more
modules. A fault would pull the EN pin low, disabling all
the modules and would not creating current bounce.
Thus, no single channel would be over stressed when a
fault occurs.
Since the EN pins are pulled down under fault conditions,
the pull-up resistor (RUP) should be scaled to sink no
more than 5mA current from EN pin. Essentially, the EN
pins cannot be directly connected to VCC.
Soft-Start
The ISL8200M has an internal digital pre-charged
soft-start circuitry, which has a rise time inversely
proportional to the switching frequency and is
determined by an digital counter that increments with
every pulse of the phase clock. The full soft-start time
from 0V to 0.6V can be estimated by Equation 5.
The ISL8200M has the ability to work under a pre-
charged output. The PWM outputs will not feed to the
drivers until the first PWM pulse is seen. The low side
MOSFET is being held low for first clock cycle to provide
charge for the bootstrap capacitor. If the pre-charged
output voltage is greater than the final target level but
less than the 113% setpoint, switching will not start until
the output voltage is reduced to the target voltage and
the first PWM pulse is generated. The maximum
t
SS
Δ
R UP
V
V
EN_FTH
RAMP
=
2560
------------ -
=
f
SW
V EN_HYS
---------------------------- -
I
EN_HYS
=
=
LIMIT(V
V
EN_RTH
CC_FF
–
V
R DOWN
EN_HYS
SYSTEM DELAY
×
G
RAMP
15
FIGURE 25. SIMPLIFIED ENABLE AND VOLTAGE FEEDFORWARD CIRCUIT
=
, VCC - 1.4V - V
-------------------------------------------------------------- -
V EN_FTH V EN_REF
R
UP
•
V
–
EN_REF
RAMP_OFFSET
R
R
DOWN
UP
VIN
(EQ. 5)
ISL8200M
)
FF
EN
V
CC_FF
allowable pre-charged level is 113%. If the pre-charged
level is above 113% but below 120%, the output will
hiccup between 113% (LGATE turns on) and 87%
(LGATE turns off) while EN is pulled low. If the pre-
charged load voltage is above 120% of the targeted
output voltage, then the controller will be latched off and
not be able to power-up.
FIGURE 23. SOFT-START WITH VOUT < TARGET
FIGURE 24. SOFT-START WITH VOUT BELOW OV BUT
0.8V
OV, OT, OC, AND PLL LOCKING FAULTS
-100mV
G
-100mV
FIGURE 22. SOFT-START WITH VOUT = 0V
0.8V
RAMP
FIRST PWM PULSE
I
INIT. VOUT
EN_HYS
0.0V
FIRST PWM PULSE
= 1.25
VOLTAGE
ABOVE FINAL TARGET VOLTAGE
V
= 30µA
FIRST PWM PULSE
RAMP_OFFSET
∑
VCC - 1.4V
LIMITER
= 1.0V
384 Clock
Cycles
t
SS_DLY
SS Settling at VREF + 100mV
VOUT TARGET VOLTAGE
SS Settling at VREF + 100mV
VOUT TARGET VOLTAGE
SAWTOOTH
AMPLITUDE
(ΔV
VOUT TARGET VOLTAGE
≈
RAMP
t
----------- -
F
SS
384
SW
SOFT-START
=
)
UPPER LIMIT
OV = 113%
LOWER LIMIT
(RAMP OFFSET)
2560
------------ -
f
SW
February 26, 2010
FN6727.1