ZUP10-20/U TDK Corporation, ZUP10-20/U Datasheet - Page 52

PWR SUP BENCH PROG 0-10V 200W

ZUP10-20/U

Manufacturer Part Number
ZUP10-20/U
Description
PWR SUP BENCH PROG 0-10V 200W
Manufacturer
TDK Corporation
Series
ZUPr
Type
Enclosedr
Datasheets

Specifications of ZUP10-20/U

Number Of Outputs
1
Efficiency
77%
Voltage - Output
0 ~ 10V
Power (watts)
200W
Applications
Commercial
Power Supply Type
Switching (Closed Frame)
Voltage - Input
85 ~ 265VAC
Mounting Type
Chassis Mount
1st Output
0 ~ 10 VDC @ 20A
Size / Dimension
13.78" L x 4.88" W x 2.76" H (350mm x 124mm x 70mm)
Power (watts) - Rated
200W
Operating Temperature
0°C ~ 50°C
Approvals
CE, EN, UL
Line Regulation
0.01%
Load Regulation
0.01%
Output Current (max)
20A
Input Voltage
85 to 265V
Output Power (max)
200W
Input Frequency
47 to 63Hz
Screening Level
Commercial
Operating Temperature Min Deg. C
0C
Operating Temperature Max Deg. C
50C
Mounting Style
Desktop
Accuracy
0.02% + 8 mV
Brand/series
ZUP
Current, Output
20 A
Display Type
Digital Meter
Power, Output
200 W
Power, Rating
200 W (Max.)
Regulation, Line
0.01% + 2 mA⁄1 mV + 0.005%
Regulation, Load
0.01% + 5 mA⁄2 mV + 0.005%
Standards
UL Listed, CE Marked
Temperature Coefficient
30 ppm⁄°C (CV)⁄100 ppm⁄°C (CC)
Temperature, Operating, Maximum
50 °C
Temperature, Operating, Minimum
0 °C
Voltage, Input
85-265 VAC
Voltage, Noise
50 mV @ 20 MHz BW
Voltage, Output
10 VDC
Voltage, Ripple
5 mV @ 5 Hz to 1 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
3rd Output
-
2nd Output
-
4th Output
-
Lead Free Status / Rohs Status
RoHS Compliant part
Other names
285-1668
Q1074270
ZUP10-20/U
ZUP1020/U
2. Alarm Status Register:
The alarm status register records fault conditions occurring during power supply operation. Any set bit
in this register causes the ‘alarm’ bit in the operational status register to be set. Reading the register
does not change it’s content. The register is cleared by :DCL; command.
Table 5-6: Alarm status register content.
Notes: (*1) Since at each AC turn off the AC fail bit is generated and stored, it is recommended to
3. Error Codes Register:
The error codes register records errors that occurred during the programming of the power supply. Any
set bit in this register causes the ‘prog’ bit in the alarm status register to be set. Reading the register
does not change it’s content. The register is cleared by :DCL; command.
Table 5-7: Error codes register content.
5.5.4.2 Status control commands
Bit Name
ovp
otp
a/c fail
fold
prog
Bit Name
not used
wrong command
buffer overflow
wrong voltage
wrong current
2
#
1
Commands
:ALM?;
:STA?;
(*2) FOLD bit is automatically reset upon cancellation of FOLD protection.
(*3) OVP, OTP and ‘prog’ bits reset at AC turn-off or by :DCL; command.
send a :DCL; command following application of AC voltage to the power supply, to clear the
alarm status register.
In case the OTP or OVP is triggered, the front panel control is disabled until the AC input is
recycled by turning the AC ON/OFF switch to OFF and after approx. 10 sec. to ON.
Bit No
1
2
3
4
5
Bit No
1
2
3
4
5
‘1’ - Indicates that the over-voltage protection was tripped
‘1’ - Indicates that the over-temperature protection was tripped
‘1’ - Indicates that a failure occurred at the input voltage supply
‘1’ - Indicates that the foldback protection was activated
‘1’ - Indicates a programming error has occurred
Meaning
Reads the alarm status register content.
Returns the string AL followed by ASCII characters representing the
register’s content.
Refer to table 5-6 for the register content description.
example- AL00000
Reads the operational status register content.
Returns the string
register’s content.
Refer to table 5-5 for the register content description.
example- OS00010000
Description
‘1’ - Indicates that an unknown string was received
‘1’ - Indicates an overflow in the communication buffer
‘1’ - Indicates an attempt to program the power supply to a voltage
out of specification limits.
‘1’ - Indicates an attempt to program the power supply to a current
out of specification limits.
Meaning
OS
followed by ASCII characters representing the
(*3)
(*3)
(*1)
(*2)
(*3)

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