AD9516-3/PCBZ Analog Devices Inc, AD9516-3/PCBZ Datasheet - Page 14

• Manufacturer Part Number: AD9516-3/PCBZ
• Description: BOARD EVAL FOR AD9516-3 2.0GHZ
• Manufacturer: Analog Devices Inc

Specifications of AD9516-3/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9516-3
• Primary Attributes: 2 Inputs, 14 Outputs, 2GHz VCO
• Secondary Attributes: CMOS, LVDS, LVPECL Output Logic, ADIsimCLK™ Graphical User Interface
• Silicon Manufacturer: Analog Devices
• Application Sub Type: PLL Clock Synthesizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9516-0, AD9516-1, AD9516-2
• Silicon Family Name: AD9516-X
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9516-3
POWER DISSIPATION
Table 17.
Parameter
POWER DISSIPATION, CHIP
POWER DELTAS, INDIVIDUAL FUNCTIONS
Power-On Default
Full Operation; CMOS Outputs at 225 MHz
Full Operation; LVDS Outputs at 225 MHz
PD Power-Down
PD Power-Down, Maximum Sleep
VCP Supply
VCO Divider
REFIN (Differential)
REF1, REF2 (Single-Ended)
VCO
PLL
Channel Divider
LVPECL Channel (Divider Plus Output Driver)
LVPECL Driver
LVDS Channel (Divider Plus Output Driver)
LVDS Driver
CMOS Channel (Divider Plus Output Driver)
CMOS Driver (Second in Pair)
CMOS Driver (First in Second Pair)
Fine Delay Block
Min
20
Typ
1.0
1.6
1.6
75
31
4
30
4
70
75
30
160
90
120
50
100
0
30
50
Rev. A | Page 14 of 80
Max
1.2
185
4.8
2.2
2.3
Unit
W
W
W
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
Test Conditions/Comments
No clock; no programming; default register values;
does not include power dissipated in external resistors
PLL on; internal VCO = 2250 MHz; VCO divider = 2;
all channel dividers on; six LVPECL outputs at 562.5 MHz;
eight CMOS outputs (10 pF load) at 225 MHz; all fine delay on,
maximum current; does not include power dissipated in
external resistors
PLL on; internal VCO = 2250 MHz, VCO divider = 2;
all channel dividers on; six LVPECL outputs at 562.5 MHz;
four LVDS outputs at 225 MHz; all fine delay on, maximum
current; does not include power dissipated in external
resistors
PD pin pulled low; does not include power dissipated
in terminations
PD pin pulled low; PLL power-down, Register 0x010[1:0] = 01b;
SYNC power-down, Register 0x230[2] = 1b; REF for distribution
power-down, Register 0x230[1] = 1b
PLL operating; typical closed loop configuration
Power delta when a function is enabled/disabled
VCO divider bypassed
All references off to differential reference enabled
All references off to REF1 or REF2 enabled; differential
reference not enabled
CLK input selected to VCO selected
PLL off to PLL on, normal operation; no reference enabled
Divider bypassed to divide-by-2 to divide-by-32
No LVPECL output on to one LVPECL output on,
independent of frequency
Second LVPECL output turned on, same channel
No LVDS output on to one LVDS output on; see Figure 8 for
dependence on output frequency
Second LVDS output turned on, same channel
Static; no CMOS output on to one CMOS output on;
see Figure 9 for variation over output frequency
Static; second CMOS output, same pair, turned on
Static; first output, second pair, turned on
Delay block off to delay block enabled; maximum current
setting