CRD8900A-1 Cirrus Logic Inc, CRD8900A-1 Datasheet - Page 19

• Manufacturer Part Number: CRD8900A-1
• Description: KIT EVAL FOR CS8900A
• Manufacturer: Cirrus Logic Inc
• Series: CrystalLAN™r

Specifications of CRD8900A-1

• Main Purpose: Interface, Ethernet
• Utilized Ic / Part: CS8900A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Other names: 598-1163

DS271F5
memory. The CS8900A has three pairs of
DMA pins that can be connected directly to the
three 16-bit DMA channels of the ISA bus.
Only one DMA channel is used at a time. It is
selected during initialization by writing the
number of the desired channel (0, 1 or 2) into
PacketPage Memory base + 0024h. Unused
DMA pins are placed in a high-impedance
state. The selected DMA request pin goes
high when the CS8900A has received frames
to transfer to the host memory via DMA. If the
DMABurst bit (register 17, BusCTL, Bit B) is
clear, the pin goes low after the DMA operation
is complete. If the DMABurst bit is set, the pin
goes low 32 µs after the start of a DMA trans-
fer.
The DMA pin pairs are arranged on the
CS8900A to facilitate board layout. Crystal
recommends the configuration in Table 3
when connecting these pins to the ISA bus.
For a description of DMA mode, see
Section 5.3 on page 90.
3.3 Reset and Initialization
3.3.1 Reset
Seven
CS8900A to reset its internal registers and cir-
cuits.
3.3.1.1 External Reset, or ISA Reset
There is a chip-wide reset whenever the RE-
SET pin is high for at least 400 ns. During a
CS8900A
Crystal LAN™ Ethernet Controller
DMARQ0 (Pin 15)
DMARQ1 (Pin 13)
DMACK0 (Pin 16)
DMACK1 (Pin 14)
DMARQ2 (Pin 11)
DMACK2 (Pin 12)
CS8900A DMA
Signal (Pin #)
different
Table 3. DMA Assignments
ISA DMA
conditions
DACK5
DACK6
DACK7
Signal
DRQ5
DRQ6
DRQ7
CIRRUS LOGIC PRODUCT DATASHEET
base + 0024h
PacketPage
cause
0000h
0001h
0002h
the
chip-wide reset, all circuitry and registers in
the CS8900A are reset.
3.3.1.2 Power-Up Reset
When power is applied, the CS8900A main-
tains reset until the voltage at the supply pins
reaches approximately 2.5 V. The CS8900A
comes out of reset once Vcc is greater than
approximately 2.5 V and the crystal oscillator
has stabilized.
3.3.1.3 Power-Down Reset
If the supply voltage drops below approximate-
ly 2.5 V, there is a chip-wide reset. The
CS8900A comes out of reset once the power
supply returns to a level greater than approxi-
mately 2.5 V and the crystal oscillator has sta-
bilized.
3.3.1.4 EEPROM Reset
There is a chip-wide reset if an EEPROM
checksum error is detected (see Section 3.4
on page 21).
3.3.1.5 Software Initiated Reset
There is a chip-wide reset whenever the RE-
SET bit (Register 15, SelfCTL, Bit 6) is set.
3.3.1.6 Hardware (HW) Standby or Suspend
The CS8900A goes though a chip-wide reset
whenever it enters or exits either HW Standby
mode or HW Suspend mode (see Section 3.7
on page 27 for more information about HW
Standby and Suspend).
3.3.1.7 Software (SW) Suspend
Whenever the CS8900A enters SW Suspend
mode, all registers and circuits are reset ex-
cept for the ISA I/O Base Address register (lo-
cated at PacketPage base + 0020h) and the
SelfCTL register (Register 15). Upon exit,
there is a chip-wide reset (see Section 3.7 on
page 27 for more information about SW Sus-
pend).
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