CRD8900A-1 Cirrus Logic Inc, CRD8900A-1 Datasheet - Page 38

• Manufacturer Part Number: CRD8900A-1
• Description: KIT EVAL FOR CS8900A
• Manufacturer: Cirrus Logic Inc
• Series: CrystalLAN™r

Specifications of CRD8900A-1

• Main Purpose: Interface, Ethernet
• Utilized Ic / Part: CS8900A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Other names: 598-1163

squelch threshold (either positive or negative,
depending on polarity) is rejected.
3.11.3.2 Extended Range
The CS8900A supports an Extended Range
feature that reduces the 10BASE-T receive
squelch threshold by approximately 6 dB. This
allows the CS8900A to operate with 10BASE-
T cables that are longer than 100 meters (100
meters is the maximum length specified by the
Ethernet standard). The exact additional dis-
tance depends on the quality of the cable and
the amount of electromagnetic noise in the
surrounding environment. To activate this fea-
ture, the host must set the LoRxSquelch bit
(Register 13, LineCTL, Bit E).
3.11.4 Link Pulse Detection
To prevent disruption of network operation due
to a faulty link segment, the CS8900A continu-
ally monitors the 10BASE-T receive pair
(RXD+/ RXD-) for packets and link pulses. Af-
ter each packet or link pulse is received, an in-
ternal Link-Loss timer is started. As long as a
packet or link pulse is received before the Link-
Loss timer finishes (between 25 and 150 ms),
the CS8900A maintains normal operation. If
no receive activity is detected, the CS8900A
disables packet transmission to prevent “blind”
transmissions onto the network (link pulses
are still sent while packet transmission is dis-
abled). To reactivate transmission, the receiv-
er must detect a single packet (the packet itself
is ignored), or two link pulses separated by
38
Time
Packet
Less Than
CIRRUS LOGIC PRODUCT DATASHEET
16ms
Figure 14. Link Pulse Transmission
Packet
more than 2 to 7 ms and no more than 25 to
150 ms (see Section 7.4 on page 114 for
10BASE-T timing).
The state of the link segment is reported in the
LinkOK bit (Register 14, LineST, Bit 7). If the
HC0E bit (Register 15, SelfCTL, Bit D) is clear,
it is also indicated by the output of the LIN-
KLED pin. If the link is “good”, the LinkOK bit is
set and the LINKLED pin is driven low. If the
link is “bad” the LinkOK bit is clear and the LIN-
KLED pin is high. To disable this feature, the
host must set the DisableLT bit (Register 19,
TestCTL, Bit 7). If DisableLT is set, the
CS8900A will transmit and receive packets in-
dependent of the link segment.
3.11.5 Receive Polarity Detection and Cor-
rection
The CS8900A automatically checks the polar-
ity of the receive half of the twisted pair cable.
If the polarity is correct, the PolarityOK bit
(Register 14, LineST, bit C) is set. If the polar-
ity is reversed, the PolarityOK bit is clear. If the
PolarityDis bit (Register 13, LineCTL, Bit C) is
clear, the CS8900A automatically corrects a
reversal. If the PolarityDis bit is set, the
CS8900A does not correct a reversal. The Po-
larityOK bit and the PolarityDis bit are inde-
pendent.
To detect a reversed pair, the receiver exam-
ines received link pulses and the End-of-
Frame (EOF) sequence of incoming packets.
If it detects at least one reversed link pulse and
16ms
Crystal LAN™ Ethernet Controller
Pulse
Link
16ms
CS8900A
Pulse
Link
DS271F5