CRD8900A-1 Cirrus Logic Inc, CRD8900A-1 Datasheet - Page 64

• Manufacturer Part Number: CRD8900A-1
• Description: KIT EVAL FOR CS8900A
• Manufacturer: Cirrus Logic Inc
• Series: CrystalLAN™r

Specifications of CRD8900A-1

• Main Purpose: Interface, Ethernet
• Utilized Ic / Part: CS8900A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Other names: 598-1163

4.4.18 Register 15: Self Control
(SelfCTL, Read/Write, Address: PacketPage base + 0114h)
SelfCTL controls the operation of the LED outputs and the lower-power modes.
010101
RESET
SWSuspend
HWSleepE
HWStandbyE
HC0E
HC1E
HCB0
HCB1
After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM
is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19.
Reset value is: 0000 0000 0001 0101
64
HCB1
7
F
RESET
HCB0
Control Register.
cleared as a result of the reset.
there is a partial reset. All registers and circuits are reset except for the ISA I/O Base Address
Register and the SelfCTL Register. There is no transmit nor receive activity in this mode. To
come out of software Suspend, the host issues an I/O Write within the CS8900A's assigned I/O
space (see Section 3.7 on page 27 for a complete description of the CS8900A's low-power
modes).
ative (unless in SWSuspend mode, as shown above). If SLEEP is low, the CS8900A enters ei-
ther the Hardware Standby or Hardware Suspend mode. When clear, the CS8900A ignores the
SLEEP input pin (see Section 3.7 on page 27 for a complete description of the CS8900A's low-
power modes).
CS8900A enters the Hardware Standby mode. When clear, the CS8900A enters the Hardware
Suspend mode (see Section 3.7 on page 27 for a complete description of the CS8900A's low-
power modes).
pin is LINKLED. When HC0E is set, the output pin is HC0 and the HCB0 bit (Bit E) controls the
pin.
put pin is BSTATUS and indicates receiver ISA Bus activity. When HC1E is set, the output pin
is HC1 and the HCB1 bit (Bit F) controls the pin.
clear, HC0 is high. HC0 may drive an LED or a logic gate. When HC0E (Bit C) is clear, this con-
trol bit is ignored.
clear, HC1 is high. HC1 may drive an LED or a logic gate. When HC1E (Bit D) is clear, this con-
trol bit is ignored.
These bits provide an internal address used by the CS8900A to identify this as the Chip Self
When set, a chip-wide reset is initiated immediately. RESET is an Act-Once bit. This bit is
When set, the CS8900A enters the software initiated Suspend mode. Upon entering this mode,
When set, the SLEEP input pin is enabled. If SLEEP is high, the CS8900A is "awake", or oper-
If HWSleepE is set and the SLEEP input pin is low, then when HWStandbyE is set, the
The LINKLED or HC0 output pin is selected with this control bit. When HC0E is clear, the output
The BSTATUS or HC1 output pin is selected with this control bit. When HC1E is clear, the out-
When HC0E (Bit C) is set, this bit controls the HC0 pin. If HCB0 is set, HC0 is low. If HCB0 is
When HC1E (Bit D) is set, this bit controls the HC1 pin. If HCB1 is set, HC1 is low. If HCB1 is
E
6
HC1E
D
5
CIRRUS LOGIC PRODUCT DATASHEET
HC0E
C
4
B
3
010101
HW Standby
Crystal LAN™ Ethernet Controller
A
2
HWSleepE
1
9
SW Suspend
CS8900A
DS271F5
0
8