CRD8900A-1 Cirrus Logic Inc, CRD8900A-1 Datasheet - Page 98

• Manufacturer Part Number: CRD8900A-1
• Description: KIT EVAL FOR CS8900A
• Manufacturer: Cirrus Logic Inc
• Series: CrystalLAN™r

Specifications of CRD8900A-1

• Main Purpose: Interface, Ethernet
• Utilized Ic / Part: CS8900A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Other names: 598-1163

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5.5.4 Keeping StreamTransfer Mode
Active
When the CS8900A initiates a StreamTransfer
cycle, it will continue to execute cycles as long
as the following conditions hold true:
•
Interrupt
Request
Interrupt
Request
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updates the DMA Start-of-Frame register
(PacketPage base + 0026h);
updates the DMA Frame Count register
(PacketPage base + 0028h);
updates DMA Byte Count register (Packet-
Page base + 002Ah);
sets the RxDMAFrame bit (Register C,
BufEvent, Bit 7); and,
generates an RxDMAFrame interrupt.
all packets received are of legal length with
valid CRC;
4 Back-to-Back Frames
4 Back-to-Back Frames
Figure 28. Receive Example Without Stream Transfer
Figure 29. Receive DMA Configuration Options
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9 Interrupts for 9 "Good" Packets
2 Interrupts for 9 "Good" Packets
T > 52 us
T > 52 us
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If any of these conditions are not met, the
CS8900A exits StreamTransfer by generating
RxOK and RxDMA interrupts. The CS8900A
then returns to either Memory, I/O, or DMA
mode, depending on configuration.
5.5.5 Example of StreamTransfer
Figure 28 shows how four back-to-back
frames, followed by five back-to-back frames,
would be received without StreamTransfer.
Figure 29 shows how the same sequence of
frames would be received with StreamTrans-
fer.
each packet follows its predecessor by less
than 52 ms; and,
the DA of each packet passes the DA filter.
Crystal LAN™ Ethernet Controller
5 Back-to-Back Frames
5 Back-to-Back Frames
Time
Time
CS8900A
DS271F5