CDB4955A Cirrus Logic Inc, CDB4955A Datasheet

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NTSC/PAL Digital Video Encoder Features Six DACs providing simultaneous composite,S-video, and RGB or Component YUV outputs Programmable DAC output currents for low impedance (37.5 Ω) and high impedance (150 Ω) loads Multi-standard support for NTSC-M, NTSC- JAPAN, PAL (B, D, ...

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ORDERING INFORMATION Product Description CS4954 NTSC/PAL Digital Video Encoder CS4955 CDB4954/55 CS4954/55 Evaluation Board 2 Package Pb-Free Grade 48-TQFP Yes Commercial -40º to +85º CS4954 CS4955 Temp Range Container Order# CS4954-CQZ Rail CS4955-CQZ - - CDB4954A/55A DS278F6 ...

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TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................................6 AC & DC PARAMETRIC SPECIFICATIONS ............................................................................................6 RECOMMENDED Operating Conditions .......................................................................................................6 THERMAL CHARACTERISTICS ..............................................................................................................6 DC CHARACTERISTICS ..........................................................................................................................6 AC CHARACTERISTICS ..........................................................................................................................8 TIMING CHARACTERISTICS ...................................................................................................................9 2. ADDITIONAL CS4954/5 FEATURES .....................................................................................................11 3. CS4954 INTRODUCTION ......................................................................................................................11 4. ...

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Green DAC ....................................................................................................................... 33 7.4.6 Blue DAC .......................................................................................................................... 33 7.4.7 DAC Useage Rules ........................................................................................................... 34 8. PROGRAMMING ................................................................................................................................... 34 8.1 Host Control Interface .................................................................................................................. 34 8.1.1 I²C® Interface ................................................................................................................... 34 8.1.2 8-bit Parallel Interface ....................................................................................................... 35 8.2 Register Description ...

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LIST OF FIGURES Figure 1. Video Pixel Data and Control Port Timing ..................................................................8 Figure 2. I²C Host Port Timing ...................................................................................................9 Figure 3. Reset Timing.............................................................................................................10 Figure 4. ITU R.BT601 Input Slave Mode Horizontal Timing ...................................................16 Figure 5. ITU R.BT601 Input Master ...

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CHARACTERISTICS AND SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS AC & DC PARAMETRIC SPECIFICATIONS Parameter Power Supply Input Current Per Pin (Except Supply Pins) Output Current Per Pin (Except Supply Pins) Analog Input Voltage Digital Input Voltage Ambient Temperature Power Applied Storage ...

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Parameter Low Level Output Voltage SDA pin only 6mA Output Leakage Current High-Z Digital Outputs Analog Outputs Full Scale Output Current CVBS/Y/C/R/G/B Full Scale Output Current CVBS/Y/C/R/G/B LSB Current CVBS/Y/C/R/G/B LSB Current CVBS/Y/C/R/G/B DAC-to-DAC Matching Output Compliance Output ...

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AC CHARACTERISTICS Parameter Pixel Input and Control Port (Figure 1) Clock Pulse High Time Clock Pulse Low Time Clock to Data Set-up Time Clock to Data Hold Time Clock to Data Output Delay CLK T ch V[7:0] HSYNC/VSYNC (Inputs) HSYNC/VSYNC ...

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TIMING CHARACTERISTICS Parameter I²C Host Port Timing (Figure 2) SCL Frequency Clock Pulse High Time Clock Pulse Low Time Hold Time (Start Cond.) Setup Time (Start Cond.) Data Setup Time Rise Time Fall Time Setup Time (Stop Cond.) Bus Free ...

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TIMING CHARACTERISTICS Parallel Host Port Timing (Figure 27, 28, 29) Read Cycle Time Read Pulse Width Address Setup Time Read Address Hold Time Read Data Access Time Read Data Hold Time Write Recovery Time Write Pulse Width Write Data Setup ...

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ADDITIONAL CS4954/5 FEATURES • Five programmable DAC output combinations, including YUV and second composite • Optional pseudo-progressive scan @ MPEG2 field rates • Stable color subcarrier for MPEG2 systems • General purpose input and output pins • Individual DAC ...

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The CS4954/5 is designed to function as a video timing master or video timing slave. In both Master and Slave Modes, all timing is sampled and assert- ed with the rising edge of the CLK pin. In most cases, the ...

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U_AMP and V_AMP 8-bit host addressable registers. The U and V chroma signals are fed to a quadrature modulator in which they are combined with the output ...

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DAC Pin # CVBS the six DACs has its own associated DAC enable bit. In the Disable Mode, the 10-bit DACs source (or sink) zero current. When running the ...

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Teletext Services The CS4954/5 encodes the most common teletext formats, such as European Teletext, World Stan- dard Teletext (PAL and NTSC), and North Ameri- can Teletext (NABTS). Teletext data can be inserted in any of the TV lines (blanking ...

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NTSC 27MHz Clock Count 1682 1683 1684 PAL 27MHz Clock Count 1702 1703 1704 CLK HSYNC (input) V[7: (SYNC_DLY=0) active pixel • • • #720 V[7: (SYNC_DLY=1) active pixel active pixel #719 Figure 4. ...

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PROG_VS Register (0x0D). VSYNC can be de- layed by thirteen lines or advanced by eighteen lines. 5.2.3 Vertical Timing The CS4954/5 can be configured to operate in any of four different timing modes: PAL, which is 625 vertical lines, 25 ...

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NTSC Vertical Timing (odd field) Line HSYNC VSYNC FIELD NTSC Vertical Timing (even field) Line HSYNC VSYNC FIELD PAL Vertical Timing (odd field) Line HSYNC VSYNC FIELD PAL Vertical Timing (even field) Line HSYNC VSYNC FIELD VSYNC stays low for ...

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Analog Field 1 523 524 525 1 Analog Field 2 261 262 263 Analog Field 3 523 524 525 1 Analog Field 4 261 262 263 Burst begins with positive half-cycle Field two begins with VSYNC transitioning low at line ...

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Burst Phase = 135 degrees relative mentioned above, there ...

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Burst begins with positive half-cycle Burst phase = reference phase = 180 relative to B-Y Figure 9. NTSC Video Non-Interlaced Progressive Scan Timing 5.4 Digital Video Input Modes ...

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Burst Phase = 135 degrees relative to U Figure 10. PAL Video Non-Interlaced Progressive Scan Timing ITU R.BT656 ...

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System Fsubcarrier NTSC-M, NTSC-J 3.5795455 MHz 43E0F83E PAL- 4.43361875 MHz 54131596 PAL-N (Argentina) 3.582056 MHz PAL-M 3.579611 MHz Table 3. 5.7 Subcarrier Compensation Since the subcarrier is synthesized from CLK, the subcarrier frequency error will ...

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As the closed caption interrupts occur, the host soft- ware responds by writing the next two bytes to be inserted to the correct ...

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TTXRQ provides a fully programmable request signal to the teletext source, indicating the insertion period of the bitstream at independently selectable lines for both TV fields. The internal insertion win- dow for text is set to either 360, 296 or ...

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Table shows how to program the TTXHS register for teletext instantiation into the analog signals for the various supported TV formats. TTXHS is the time between the leading ...

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Color Cb White 0 Yellow - 84 Cyan + 28 Green - 56 Magenta + 56 Red - 28 Blue + 84 Black 0 Table 6. Internal Color Bar Values (8-bit values, Cb/Cr are in twos complement format) 5.13 VBI ...

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GPIO_DATA_REG when it detects regis- ter address 0×0A through the I²C interface. A detection of address 0×0A can happen in two ways. The first and most common way this will happen is when address 0×0A is written to ...

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FILTER RESPONSES 1.3 Mhz. filter frequency response 0 -10 -20 -30 -40 -50 -60 - frequency (Hz) Figure 14. 1.3 MHz Chrominance low-pass filter transfer characteristic 650 Khz. filter frequency response 0 -5 -10 ...

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Chroma Output Interpolator Pass band 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0 0.5 1 1.5 2 2.5 Frequency (MHz) Figure 18. Chrominance output interpolation filter transfer characteristic (passband) Luma Output Interpolation Filter Response at 27 ...

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RGB datapath filter when rgb_bw = 1 (Reduced Bandwidth) (-3 dB) 1 0.5 0 -0.5 -1 -1 Frequency (MHz) Figure 22. Chroma Interpolator for RGB Datapath when rgb_bw=1 (Reduced Bandwidth) RGB datapath filter ...

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ANALOG 7.1 Analog Timing All CS4954/5 analog timing and sequencing is de- rived from the 27 MHz clock input. The analog out- puts are controlled internally by the video timing generator in conjunction with master and slave tim- ing. ...

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Chrominance DAC The C output pin is driven from a 10-bit 27 MHz current output DAC that internally receives the C or chrominance portion of the video signal (color only). The C DAC is designed to drive proper video ...

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To completely dis- able or for low power device operation, the blue DAC can be totally shut down via the B_PD con- trol register bit in Control Register 4 (0×04). In this mode turn-on using ...

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PDAT [7:0] are available to be used for GPIO operation in I²C host interface SDA SCL A 1-7 Start Address R/W Note: I²C transfers data always with MSB first, LSB last 8.1.2 8-bit Parallel Interface ...

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RD PADR PDAT[7:0] Figure 28. 8-bit Parallel Host Port Timing: Address Read Cycle WR PADR PDAT[7:0] Figure 29. 8-bit Parallel Host Port Timing: Address Write Cycle 8.2 Register Description A set of internal registers are available for control- ling the ...

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Address × × × × × × × × × × × × × ...

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Address × × × × × × Control Register 0 × Address 0 00 CONTROL_0 Bit Number 7 Bit Name TV_FMT Default 0 Bit Mnemonic selects ...

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Bit Mnemonic chroma lpf bandwidth (0 = 650 kHz 1.3 MHz chroma lpf on/off (0 = off on) 4 LPF Full bandwidth on RGB reduced to 2.5 ...

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Control Register 2 × Address 0 02 CONTROL_2 Bit Number 7 Bit Name OUTPUT FORMAT Default 0 Bit Mnemonic 7:5 OUTPUT FORMAT 4 TTX WST 3 TTX EN 2 SYNC DLY 1 XTAL 0 BU DIS 40 Read/Write Default Value ...

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Control Register 3 × Address 0 03 CONTROL_3 Bit Number 7 Bit Name RESERVED Default 0 Bit Mnemonic 7 THR THR THR THR_EN 0 CBAR Control Register 4 ...

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Control Register 5 × Address 0 05 CONTROL_5 Bit Number 7 6 Bit Name RSVD LOW IMP Default 0 0 Bit Mnemonic reserved 7 - selects between tri-state output (0) or output enabled (1) mode of DACs 6 LOW IMP ...

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Background Color Register × Address 0 08 BKG_COLOR Read/Write Bit Number 7 Bit Name Default 0 Bit Mnemonic Background color ( (default is 0000 0011 - blue) 7:0 BG GPIO Control Register ...

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Sync Register 1 × Address 0 0E Sync_1 Bit Number 7 Bit Name Default 1 Bit Mnemonic 7:0 PROG HS[7:0] I²C Address Register × Address 0 0F I²C_ADR Bit Number 7 6 Bit Name RESERVED Default 0 0 Bit Mnemonic ...

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Hue LSB Adjust Register × Address 0 15 HUE_LSB Bit Number 7 Bit Name Default 0 Bit Mnemonic 8 LSBs for hue phase shift 7:0 HUE LSB Hue MSB Adjust Register × Address 0 16 HUE_MSB Bit Number 7 Bit ...

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Closed Caption Data Register × Address 0 19 CC_21_1 × CC_21_2 × CC_284_1 × CC_284_2 Bit Mnemonic first closed caption databyte of line 21 7:0 CC_21_1 second closed caption databyte of line 21 7:0 ...

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W ide Screen Signalling Register 1 × Address 0 1F WSS_REG_1 Bit Number 7 Bit Name WSS_15 WSS_14 Default 0 Bit Mnemonic 7 WSS_15 6 WSS_14 5 WSS_13 4 WSS_12 3 WSS_11 2 WSS_10 1 WSS_9 0 WSS_8 Wide Screen ...

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F ilter Register 1 × Address 0 23 CR_AMP Bit Number 7 Bit Name Default 1 Bit Mnemonic V(Cr) amplitude coefficient 7:0 V_AMP F ilter Register 2 × Address 0 24 Y_AMP Bit Number 7 Bit Name Default 1 Bit ...

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F ilter Register 5 × Address 0 27 B_AMP Bit Number 7 Bit Name Default 1 Bit Mnemonic Blue amplitude coefficient 7:0 B_AMP F ilter Register 6 × Address 0 28 Bright_Offsett Bit Number 7 Bit Name Default 0 Bit ...

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Teletext Register 2 × Address 0 2B TTXOVS Bit Number 7 Bit Name Default 0 Bit Mnemonic Start of teletext line window in odd field 7:0 TTXOVS T eletext Register 3 × Address 0 2C TTXOVE Bit Number 7 Bit ...

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Teletext Register 6 × Address 0 2F TTX_DIS1 Bit Number 7 Bit Name Default 0 Bit Mnemonic Teletext disable bits corresponding to the lines 5-12 respectively, (11111111=all eight lines are disabled), 7:0 TTX_LINE_DIS1 (MSB is for line 5, LSB is ...

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Interrupt Register 0 × Address 0 32 INT_EN Bit Number 7 Bit Name Default 0 Bit Mnemonic reserved 7:3 - interrupt enable for closed caption line 21 2 INT_21_EN interrupt enable for closed caption line 284 1 INT_284_EN interrupt enable ...

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BOARD DESIGN AND LAYOUT CONSIDERATIONS The printed circuit layout should be optimized for lowest noise on the CS4954/5 placed as close to the output connectors as possible. All analog supply traces should be as short as possible to minimize ...

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This reduces the total power that the CS4954/5 re- quires, and eliminates the impedance mismatch presented by an unused connector. The analog out- puts should not overlay the analog power plane in order to maximize high frequency power supply re- ...

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Vcc 4.7 μ 26-19 Gpio port Vcc 1.5 kΩ 1.5 kΩ 110 Ω I²C Controller 110 Ω 27 MHz Clock Pixel Data 8-1 DS278F6 L1 Ferrite Bead 0.1 μ VDD VAA XTALIN ...

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PIN DESCRIPTION B CVBS GNDA VAA FIELD /CB HSYNC/CB VSYNC INT TEST XTAL_OUT XTAL_IN PADR VDD GNDD ...

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Pin Name Pin Number V [7: CLK 29 PADDR 16 XTAL_IN 15 XTAL_OUT 14 10 HSYNC/CB VSYNC 11 (1) FIELD/ PDAT [7:0] 19, 20, 21, 22, 23, ...

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PACKAGE DRAWING 48L TQFP PACKAGE DRAWING D D1 DIM ∝ * Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS026 ...

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REVISION HISTORY Revision Date F1 July 1999 Initial release F2 April 2004 Corrected List of Figures F3 September 2004 Added lead free package option (CS4955). Updated ordering information. Added lead-free package for CS4954; deleted CQ F4 August 2005 packages; ...

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Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in ...