CDB4955A Cirrus Logic Inc, CDB4955A Datasheet - Page 13

• Manufacturer Part Number: CDB4955A
• Description: EVALUATION BOARD FOR CS4955A
• Manufacturer: Cirrus Logic Inc

Specifications of CDB4955A

• Main Purpose: Video, Video Processing
• Embedded: Yes, Other
• Utilized Ic / Part: CS4955
• Primary Attributes: NTSC/PAL Digital Video Encoder
• Secondary Attributes: Graphical User Interface, RS-232 Interface
• Operating Frequency: 27 MHz
• Interface Type: RS-232, Composite, RGB, S-Video
• Operating Supply Voltage: 3.3 V, 5 V
• Software: Software Included
• Silicon Manufacturer: Cirrus Logic
• Silicon Core Number: CS4955
• Kit Application Type: Audio / Video / TV
• Application Sub Type: Encoder / Decoder
• Kit Contents: Evaluation Board
• Rohs Compliant: No
• For Use With/related Products: CS4954
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

able gain amplifiers in which the chroma amplitude
can be varied via the U_AMP and V_AMP 8-bit
host addressable registers.
The U and V chroma signals are fed to a quadrature
modulator in which they are combined with the
output from the subcarrier synthesizer to produce
the proper modulated chrominance signal.
The chroma is then interpolated by a factor of two
in order to operate the output DACs at twice the
pixel rate. The interpolation filters enable running
the DACs at twice the pixel rate which helps reduce
the sinx/x roll-off for higher frequencies and reduc-
es the complexity of the external analog low pass
filters.
4.5
Along with the chroma output path, the CS4954/5
Video Input Formatter has a parallel luma data out-
put to a digital delay line. The delay line is a digital
FIFO. The FIFO depth matches the clock period
delay associated with the more complex chroma
path. Brightness adjustment is also provided via the
8-bit BRIGHTNESS_OFFSET Register.
Following the luma delay, the data is passed
through an interpolation filter that has a program-
mable bandwidth, followed by a variable gain am-
plifier. The amplifier DC luma gain can be changed
using the the Y_AMP Register.
The output of the luma amplifier connects to the
sync insertion block. Sync insertion is accom-
plished by multiplexing, into the luma data path,
the different sync DC values at the appropriate
times. The digital sync generator takes horizontal
sync and vertical sync timing signals and generates
the appropriate composite sync timing (including
vertical equalization and serration pulses), blank-
ing information, and burst flag. The sync edge rates
conform to RS-170A or ITU R.BT601 and ITU
R.BT470 specifications.
It is also possible to delay the luminance signal,
with respect to the chrominance signal, by up to
DS278F6
Luma Path
three pixel clocks. This variable delay is useful to
offset different propagation delays of the luma
baseband and modulated chroma signals. This ad-
justable luma delay is available only on the
CVBS_1 output.
4.6
The RGB datapath has the same latency as the luma
and chroma path. Therefore all six simultaneous
analog outputs are synchronized. The 4:2:2 YCbCr
data is first interpolated to 4:4:4 and then interpo-
lated to 27 MHz. The color space conversion is per-
formed at 27 MHz. The coefficients for the color
space conversion conform to the ITU R.BT601
specifications.
After color space conversion, the amplitude of each
component can be independently adjusted via the
R_AMP, G_AMP, and B_AMP 8-bit host address-
able registers. A synchronization signal can be add-
ed to either one, two or all of the RGB signals. The
synchronization signal conforms to NTSC or PAL
specifications.
Some applications (e.g., projection TVs) require
analog component YUV signals. The chip provides
a programmable mode that outputs component
YUV data. Sync can be added to the luminance sig-
nal. Independent gain adjustment of the three com-
ponents is provided as well.
4.7
The CS4954/5 provides six discrete 27 MHz DACs
for analog video. The default configuration is one
10-bit DAC for S-video chrominance, one 10-bit
DAC for S-Video luminance, one 10-bit DAC for
composite output, and three 10-bit DACs for RGB
outputs. All six DACs are designed for driving ei-
ther low-impedance loads (double terminated
75 Ω) or high-impedance loads (double terminated
300 Ω). There are five different DAC configura-
tions to choose from (see Table 1, below).
The DACs can be put into high-impedance mode
via host-addressable control register bits. Each of
RGB Path and Component YUV Path
Digital to Analog Converters
CS4954 CS4955
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