CDB4955A Cirrus Logic Inc, CDB4955A Datasheet - Page 18

• Manufacturer Part Number: CDB4955A
• Description: EVALUATION BOARD FOR CS4955A
• Manufacturer: Cirrus Logic Inc

Specifications of CDB4955A

• Main Purpose: Video, Video Processing
• Embedded: Yes, Other
• Utilized Ic / Part: CS4955
• Primary Attributes: NTSC/PAL Digital Video Encoder
• Secondary Attributes: Graphical User Interface, RS-232 Interface
• Operating Frequency: 27 MHz
• Interface Type: RS-232, Composite, RGB, S-Video
• Operating Supply Voltage: 3.3 V, 5 V
• Software: Software Included
• Silicon Manufacturer: Cirrus Logic
• Silicon Core Number: CS4955
• Kit Application Type: Audio / Video / TV
• Application Sub Type: Encoder / Decoder
• Kit Contents: Evaluation Board
• Rohs Compliant: No
• For Use With/related Products: CS4954
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

VSYNC stays low for 2.5 line-times and transitions
high with the beginning of line 315. Video input on
the V [7:0] pins is expected between line 336
through line 622.
5.2.7 Progressive Scan
The CS4954/5 supports a pseudo-progessive scan
mode for which “odd” and “even” numbered line
information is presented in “odd” numbered line
positions by varying the vertical blanking timing.
This preserves precise MPEG-2 frame rates of 30
and 25 frames per second. This mode is in contrast
to other digital video encoders, which commonly
support progressive scan by repetitively displaying
18
HSYNC
HSYNC
HSYNC
HSYNC
VSYNC
VSYNC
VSYNC
VSYNC
FIELD
FIELD
FIELD
FIELD
Line
Line
Line
Line
NTSC Vertical Timing (odd field)
NTSC Vertical Timing (even field)
PAL Vertical Timing (even field)
PAL Vertical Timing (odd field)
3
264
265
311
265
1
312
4
Figure 6. Vertical Timing
266
2
313
5
267
3
314
6
a 262 line field (524/525 lines for NTSC). The
common method is flawed: over time, the output
display rate will overrun a system-clock-locked
MPEG-2 decompressor and display a field twice
every 8.75 seconds.
5.2.8 NTSC Progressive Scan
VSYNC will transition low at line four to begin
field one and will remain low for three lines or
2574 pixel cycles (858 × 3). NTSC interlaced tim-
ing is illustrated in Figure 9. In this mode, the
CS4954/5 expects digital video input at the V [7:0]
pins for 240 lines beginning on active video line 22
and continuing through line 261.
268
4
315
7
269
5
316
8
9
270
6
317
CS4954 CS4955
10
271
7
318
DS278F6