CDB4955A Cirrus Logic Inc, CDB4955A Datasheet - Page 35

• Manufacturer Part Number: CDB4955A
• Description: EVALUATION BOARD FOR CS4955A
• Manufacturer: Cirrus Logic Inc

Specifications of CDB4955A

• Main Purpose: Video, Video Processing
• Embedded: Yes, Other
• Utilized Ic / Part: CS4955
• Primary Attributes: NTSC/PAL Digital Video Encoder
• Secondary Attributes: Graphical User Interface, RS-232 Interface
• Operating Frequency: 27 MHz
• Interface Type: RS-232, Composite, RGB, S-Video
• Operating Supply Voltage: 3.3 V, 5 V
• Software: Software Included
• Silicon Manufacturer: Cirrus Logic
• Silicon Core Number: CS4955
• Kit Application Type: Audio / Video / TV
• Application Sub Type: Encoder / Decoder
• Kit Contents: Evaluation Board
• Rohs Compliant: No
• For Use With/related Products: CS4954
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

must be tied to ground. PDAT [7:0] are available to
be used for GPIO operation in I²C host interface
8.1.2 8-bit Parallel Interface
The CS4954/5 is equipped with a full 8-bit parallel
microprocessor write and read control port. Along
with the PDAT [7:0] pins, the control port interface
is comprised of host read (RD) and host write (WR)
active low strobes and host address enable
(ADDR), which, when low, enables unique address
register accesses. The control port is used to access
internal registers which configure the CS4954/5 for
various modes of operation. The internal registers
are uniquely addressed via an address register. The
DS278F6
SDA
SCL
Start
A
WR
RD
Address
Figure 27. 8-bit Parallel Host Port Timing: Read-Write/Write-Read Cycle
1-7
Note: I²C transfers data always with MSB first, LSB last
R/W
8
ACK
T
9
rec
Figure 26. I²C Protocol
1-7
Data
8
mode. For 3.3 V operation it is necessary to have
the appropriate level shifting for I²C signals.
address register is accessed during a host write cy-
cle when the WR and ADDR pins set low. Host
write cycles with ADDR set high will write 8-bit
data to the PDAT [7:0] pins into the register cur-
rently selected by the address register. Likewise
read cycles occuring with RD set low and ADDR
set high will return the register contents selected by
the address register. Reference the detailed electri-
cal timing parameter section of this data sheet for
exact host parallel interface timing characteristics
and specifications.
ACK
9
1-7
T
rec
Data ACK
8
CS4954 CS4955
9
Stop
P
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