SI3220PPT0-EVB Silicon Laboratories Inc, SI3220PPT0-EVB Datasheet - Page 4
![no-image](/images/manufacturer_photos/0/6/609/silicon_laboratories_inc_sml.jpg)
SI3220PPT0-EVB
Manufacturer Part Number
SI3220PPT0-EVB
Description
BOARD EVAL W/SI3200 INTERFACE
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Datasheet
1.SI3200-G-FSR.pdf
(112 pages)
Specifications of SI3220PPT0-EVB
Main Purpose
Interface, Analog Front End (AFE)
Utilized Ic / Part
Si3220
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Table 1. Absolute Maximum Ratings and Thermal Information
Si3220/25 Si3200/02
1. Electrical Specifications
4
Si3220/Si3225
Supply Voltage
STIPAC, STIPDC, SRINGAC, SRINGDC Current
Input Current, Digital Pins
Input Voltage, Digital Pins
Analog Ground Differential Voltage
(GND1 to ePad, GND2 to ePad or GND1 to GND2)
Digital Ground Differential Voltage
(GND3 to GND4)
Si3200
Supply Voltage
High Battery Supply Voltage
Low Battery Supply Voltage
TIP or RING Voltage
TIP or RING Current
Si3202
Supply Voltage
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded, and exposure to absolute
2. The PCB pad placed under the device package must be connected with multiple vias to the PCB ground layer and to
3. On Si3200 revision E, the dv/dt of the voltage applied to the V
4. Operation of the Si3220/Si3225 above 125 °C junction temperature may degrade device reliability. The Si3200/Si3202
5. The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layout
maximum rating conditions for extended periods may affect device reliability. Functional operation should be restricted
to the conditions as specified in the operational sections of this data sheet.
the GND1-GND4 pins via short traces. The TQFP-64 e-Pad must be properly soldered to the PCB pad during PCB
assembly. This type of low-impedance grounding arrangement is necessary to ensure that maximum differentials are
not exceeded under any operating condition in addition to providing thermal dissipation.
should be operated at a junction temperature below 140 °C for optimal reliability.
guidelines are followed correctly. The specified performance requires that the exposed pad be soldered to an exposed
copper surface of equal size and that multiple vias are added to enable heat transfer between the top-side copper
surface and a large internal copper ground plane. Refer to “AN55: Dual ProSLIC
evaluation board data sheet for specific layout examples.
2
Parameter
3
2
Rev. 1.3
I
Symbol
TIP
V
V
V
V
V
V
V
V
V
V
BATH
RING
, I
BATL
DD1-
I
BAT
DD4
IND
TIP
IN
DD
DD
RING
,
,
BAT
, V
Test Condition
Pulse < 10 us
BATH
Pulse < 4 us
Continuous
Continuous
Continuous
∆V
∆V
10 ms
1
, and V
GNDA
GNDD
BATL
®
User Guide” or to the Si3220/3225
pins must be limited to 10 V/µs.
V
V
BATH
BATH
V
–104
–109
–104
–100
–0.5
–0.3
–0.5
–0.5
Min
–20
–10
–50
–50
BATH
–15
–35
V
DDD
+100
Max
+20
+10
+50
+50
6.0
6.0
0.4
0.4
0.4
0.4
0.4
0.4
6.0
+0.3
Unit
mA
mA
mV
mV
mA
V
V
V
V
V
V
V
V
V
V
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