EVAL-AD7693CBZ Analog Devices Inc, EVAL-AD7693CBZ Datasheet - Page 18

• Manufacturer Part Number: EVAL-AD7693CBZ
• Description: BOARD EVALUATION FOR AD7693
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7693CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 500k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 18mW @ 500kSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7693
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7693
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7693 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 36, and the
corresponding timing is given in Figure 37.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.
When the conversion is complete, SDO goes from high
ACQUISITION
SDI = 1
CNV
SCK
SDO
t
CNVH
CONVERSION
Figure 37. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
t
CONV
VIO
SDI
Figure 36. CS Mode, 3-Wire with Busy Indicator
AD7693
CNV
SCK
Connection Diagram (SDI High)
1
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t
SDO
HSDO
D15
2
t
CYC
VIO
ACQUISITION
D14
impedance to low impedance. With a pull-up on the SDO line,
this transition can be used as an interrupt signal to initiate the
data reading controlled by the digital host. The AD7693 then
enters the acquisition phase and powers down. The data bits are
clocked out, MSB first, by subsequent SCK falling edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge will allow a faster reading rate, provided it has an
acceptable hold time. After the optional 17
when CNV goes high (whichever occurs first), SDO returns to
high impedance.
If multiple AD7693s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
t
3
ACQ
t
DSDO
CONVERT
DATA IN
IRQ
CLK
DIGITAL HOST
t
SCKL
t
SCKH
15
t
SCK
16
D1
17
D0
t
DIS
th
SCK falling edge or