EVAL-AD7693CBZ Analog Devices Inc, EVAL-AD7693CBZ Datasheet - Page 21

• Manufacturer Part Number: EVAL-AD7693CBZ
• Description: BOARD EVALUATION FOR AD7693
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7693CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 500k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 18mW @ 500kSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7693
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7693s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7693s is shown in
Figure 42, and the corresponding timing is given in Figure 43.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
SDO
ACQUISITION
SDI
A
t
HSCKCNV
= SDI
CNV
SCK
SDO
A
= 0
B
B
CONVERSION
t
SSCKCNV
t
CONV
t
EN
SDI
t
t
HSDO
DSDO
AD7693
Figure 43. Chain Mode Without Busy Indicator Serial Interface Timing
Figure 42. Chain Mode Without Busy Indicator Connection Diagram
CNV
SCK
A
D
D
1
A
B
15
15
t
SSDISCK
SDO
D
D
2
A
B
14
14
D
D
3
A
B
13
13
Rev. 0 | Page 21 of 24
t
SCKL
SDI
t
HSDISCK
14
AD7693
CNV
SCK
B
t
D
D
15
CYC
A
B
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7693 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are clocked by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N clocks are required to
read back the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge will allow a faster
reading rate and consequently more AD7693s in the chain,
provided the digital host has an acceptable hold time. The
maximum conversion rate can be reduced due to the total
readback time.
1
1
ACQUISITION
t
SDO
SCK
t
SCKH
t
D
D
ACQ
16
A
B
0
0
D
17
A
15
CONVERT
DATA IN
CLK
D
DIGITAL HOST
18
A
14
30
D
31
A
1
D
32
A
0
AD7693