EVAL-AD7693CBZ Analog Devices Inc, EVAL-AD7693CBZ Datasheet - Page 19

• Manufacturer Part Number: EVAL-AD7693CBZ
• Description: BOARD EVALUATION FOR AD7693
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7693CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 500k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 18mW @ 500kSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7693
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7693s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7693s is shown in
Figure 38, and the corresponding timing is given in Figure 39.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
SDI(CS1)
SDI(CS2)
ACQUISITION
SDO
CNV
SCK
t
SSDICNV
t
HSDICNV
CONVERSION
t
CONV
t
EN
SDI
AD7693
Figure 39. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
Figure 38. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
D15
CNV
SCK
1
t
HSDO
D14
SDO
2
D13
3
t
DSDO
t
SCKL
t
SCKH
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14
SDI
t
SCK
AD7693
15
D1
CNV
SCK
t
CYC
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7693 enters
the acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate, provided it has an acceptable hold time. After the
16
first), SDO returns to high impedance and another AD7693 can
be read.
16
D0
ACQUISITION
th
SDO
SCK falling edge or when SDI goes high (whichever occurs
t
ACQ
D16
17
CS2
CS1
CONVERT
DATA IN
CLK
DIGITAL HOST
D15
18
30
31
D1
32
D0
t
DIS
AD7693