ISL8201MEVAL1Z Intersil, ISL8201MEVAL1Z Datasheet - Page 11

• Manufacturer Part Number: ISL8201MEVAL1Z
• Description: BOARD EVAL STEP-DOWN POL ISL8201
• Manufacturer: Intersil

Specifications of ISL8201MEVAL1Z

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.5V
• Current - Output: 10A
• Voltage - Input: 1 ~ 20 V
• Regulator Topology: Buck
• Frequency - Switching: 600kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL8201
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Lead Free Status / Rohs Status: Compliant

where ΔI
voltage, high output voltage application, such as 20V input to
5V output, the inductor ripple becomes excessive due to the
fixed internal inductor value. In such applications, the output
current will be limited from the rating to approximately 70%
of the module’s rated current.
The relationships between the external R
typical output current I
The range of allowable voltages detected (2 x I
0mV to 475mV. If the voltage drop across R
low, then this can cause almost continuous OCP tripping and
retry. It will also be very sensitive to system noise and inrush
current spikes, so it should be avoided. The maximum
usable setting is around 0.2V across R
MOSFET); values above this might disable the protection.
Any voltage drop across R
MOSFET trip point) will disable the OCP. Note that
conditions during power-up or during a retry may look
different than normal operation. During power-up in a 12V
system, the ISL8201M starts operation just above 4V; if the
supply ramp is slow, the soft-start ramp might be over well
before 12V is reached. Therefore, with low side gate drive
voltages, the r
power-up, effectively lowering the OCP trip. In addition, the
ripple current will likely be different at a lower input voltage.
Another factor is the digital nature of the soft-start ramp. On
each discrete voltage step, there is in effect, a small load
transient and a current spike to charge the output capacitors.
The height of the current spike is not controlled, however, it
is affected by the step size of the output and the value of the
output capacitors, as well as the internal error amp
compensation. Therefore, it is possible to trip the overcurrent
with inrush current, in addition to the normal load and ripple
considerations.
I
PEAK
1. The maximum r
2. The minimum I
3. Determine I
temperature
table on page 3.
OPEN
R
50k
20k
10k
(Ω)
5k
3k
2k
SET
>
I
OUT MAX
L
is the output inductor ripple current. In a high input
(
DS(ON)
PEAK
OCP (A) @ V
)
SET
+
DS(ON)
(
-------------
P
for:
of the MOSFET will be higher during
ΔI
VCC
2
OUT(MAX)
from the “Electrical Specifications”
L
13.3
12.6
10.2
11.4
7.6
6.3
4.9
)
TABLE 2.
SET
= 5V
at the highest junction
IN
11
= 12V,
that is greater than 0.3V (0.6V
OCP levels are as follows:
SET
OCP (A) @ V
SET
(0.4V across the
SET
P
values and the
VCC
SET
17.3
16.6
14.9
13.3
10.3
8.3
6.7
is set too
= 12V
x R
IN
SET
= 12V
(EQ. 4)
) is
ISL8201M
Figure 19 shows the output response during a retry of an
output shorted to PGND. At time T
turned off due to sensing an overcurrent condition. There are
two internal soft-start delay cycles (T
MOSFETs to cool down in order to keep the average power
dissipation in retry at an acceptable level. At time T
output starts a normal soft-start cycle, and the output tries to
ramp. If the short is still applied and the current reaches the
I
output will shut off and return to time T
cycle. The retry period is thus two dummy soft-start cycles
plus one variable one (which depends on how long it takes to
trip the sensor each time). Figure 19 shows an example
where the output gets about half-way up before shutting
down; therefore, the retry (or hiccup) time will be around
17ms. The minimum should be nominally 13.6ms and the
maximum 20.4ms. If the short condition is finally removed,
the output should ramp up normally on the next T
Starting up into a shorted load looks the same as a retry into
that same shorted load. In both cases, OCP is always
enabled during soft-start; once it trips, it will go into retry
(hiccup) mode. The retry cycle will always have two dummy
time-outs, plus whatever fraction of the real soft-start time
passes before the detection and shutoff. At that point, the
logic immediately starts a new two dummy cycle time-out.
Input Voltage Considerations
Figure 12 shows a standard configuration where P
either 5V (±10%) or 12V (±20%). In each case, the gate
drivers use the P
gate driver. In addition, P
from 6.5V up to the 14.4V maximum. The P
between 5.5V and 6.5V is not allowed for long-term reliability
reasons, but transitions through it to voltages above 6.5V are
acceptable.
There is an internal 5V regulator for bias, which turns on
between 5.5V and 6.5V. Some of the delay after POR is there
to allow a typical power supply to ramp-up past 6.5V before
SET
trip point any time during the soft-start ramp period, the
FIGURE 19. OVERCURRENT RETRY OPERATION
VCC
voltage for low side gate and high side
VCC
is allowed to work anywhere
0
, the output has been
1
and T
0
for another delay
VCC
2
) to allow the
range
October 21, 2010
2
VCC
2
cycle.
, the
FN6657.2
is