ISL8201MEVAL1Z Intersil, ISL8201MEVAL1Z Datasheet - Page 8

• Manufacturer Part Number: ISL8201MEVAL1Z
• Description: BOARD EVAL STEP-DOWN POL ISL8201
• Manufacturer: Intersil

Specifications of ISL8201MEVAL1Z

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.5V
• Current - Output: 10A
• Voltage - Input: 1 ~ 20 V
• Regulator Topology: Buck
• Frequency - Switching: 600kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL8201
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Lead Free Status / Rohs Status: Compliant

Applications Information
The typical ISL8201M application schematic for input voltage
+5V or +12V is shown in Figure 11. External component
selection is primarily determined by the maximum load
current and input/output voltage.
Programming the Output Voltage
The ISL8201M has an internal 0.6V ±1.5% reference
voltage. Programming the output voltage requires a dividing
resistor (R
shown in Equation 1:
V
Note: ISL8201M has integrated 9.76kΩ resistance into the
module (dividing resistor for top side). The resistance
corresponding to different output voltages is as shown in
Table 1:
Initialization (POR and OCP Sampling)
Figure 13 shows a start-up waveform of ISL8201M. The
power-on-reset (POR) function continually monitors the bias
voltage at the PVCC pin. Once the rising POR threshold has
exceeded 4V (V
the overcurrent protection (OCP) sample and hold operation
(while COMP/EN is ~1V). When the sampling is complete,
V
OUT
OUT
V
V
R
R
begins the soft-start ramp.
=
OUT
OUT
FIGURE 13. POR AND SOFT-START OPERATION
TABLE 1. RESISTANCE TO OUTPUT VOLTAGES
FB
FB
0.6
FB
×
). The output voltage can be calculated as
⎛
⎝
1
+
PORR
9.76k
-------------- -
R
FB
4.87k
open
0.6V
1.8V
nominal), the POR function initiates
⎞
⎠
8
1.05V
3.09k
2.5V
13k
9.76k
2.16k
1.2V
3.3V
6.49k
1.33k
1.5V
(EQ. 1)
5V
ISL8201M
If the COMP/EN pin is held low during power-up, the
initialization will be delayed until the COMP/EN is released
and its voltage rises above the V
Figure 14 and Figure 15 show a typical power-up sequence
in more detail. The initialization starts at T
P
(after POR). The COMP/EN will be pulled up by an internal
20µA current source, however, the timing will not begin until
the COMP/EN exceeds the V
external capacitance of the disabling device, as well as the
compensation capacitors, will determine how quickly the
20µA current source will charge the COMP/EN pin. With
typical values, it should add a small delay compared to the
soft-start times. The COMP/EN will continue to ramp to ~1V.
From T
PVCC pin to exceed 6.5V (if rising up towards 12V), so that
the internal bias regulator can turn on cleanly. At the same
time, the ISET pin is initialized by disabling the low-side gate
driver and drawing I
This sets up a voltage that will represent the I
At T
hold operation (0.0ms to 3.4ms nominal; the longer time
occurs with the higher overcurrent setting). The sample and
hold uses a digital counter and DAC to save the voltage, so
the stored value does not degrade, as long as the P
above V
page 10 for more details on the equations and variables).
Upon the completion of sample and hold at T
operation is initiated, and the output voltage ramps up
between T
VCC
2
, there is a variable time period for the OCP sample and
rises above V
FIGURE 14. I
1
, there is a nominal 6.8ms delay, which allows the
PORR
T
4
0
and T
(See “Overcurrent Protection (OCP)” on
T
1
5
.
PORR
SET
SET
AND SOFT-START OPERATION
(nominal 21.5µA) through R
, or the COMP/EN pin is released
ENDIS
ENDIS
trip point (at T
trip point.
0
, when either
COMP/EN
3
SET
, the soft-start
October 21, 2010
1
trip point.
). The
ISET
VOUT
SETI
VCC
FN6657.2
.
is