LM3205TLEV National Semiconductor, LM3205TLEV Datasheet - Page 15

• Manufacturer Part Number: LM3205TLEV
• Description: BOARD EVALUATION LM3205TL
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM3205TLEV

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 0.8 ~ 3.6V
• Current - Output: 650mA
• Voltage - Input: 2.7 ~ 5.5V
• Regulator Topology: Buck
• Frequency - Switching: 2MHz
• Board Type: Fully Populated
• Utilized Ic / Part: LM3205
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Power - Output: -

Board Layout Considerations
The LM3205 converts higher input voltage to lower output
voltage with high efficiency. This is achieved with an inductor-
based switching topology. During the first half of the switching
cycle, the internal PMOS switch turns on, the input voltage is
applied to the inductor, and the current flows from P
to the output capacitor (C2) through the inductor. During the
second half cycle, the PMOS turns off and the internal NMOS
turns on. The inductor current continues to flow via the induc-
tor from the device PGND line to the output capacitor (C2).
Referring toFigure 4 , the LM3205 has two major current loops
where pulse and ripple current flow. The loop shown in the
BOARD LAYOUT FLOW (microSMD)
1.
2.
Minimize C1, PV
be as wide and short as possible. This is most important.
Minimize L1, C2, SW and PGND loop. These traces also
should be wide and short. This is the second priority.
IN
, and PGND loop. These traces should
FIGURE 5. Evaluation Board Layout for microSMD
FIGURE 4. Current Loop
VDD
line
15
left hand side is most important, because pulse current shown
inFigure 4 flows in this path. The right hand side is next. The
current waveform in this path is triangular, as shown in Figure
4 . Pulse current has many high-frequency components due
to fast di/dt. Triangular ripple current also has wide high-fre-
quency components. Board layout and circuit pattern design
of these two loops are the key factors for reducing noise ra-
diation and stable operation. Other lines, such as from battery
to C1(+) and C2(+) to load, are almost DC current, so it is not
necessary to take so much care. Only pattern width (current
capability) and DCR drop considerations are needed.
3.
Above layout patterns should be placed on the
component side of the PCB to minimize parasitic
inductance and resistance due to via-holes. It may be a
good idea that the SW to L1 path is routed between C2
(+) and C2(-) land patterns. If vias are used in these large
current paths, multiple via-holes should be used if
possible.
20158009
20158008
www.national.com