LM3205TLEV National Semiconductor, LM3205TLEV Datasheet - Page 16

• Manufacturer Part Number: LM3205TLEV
• Description: BOARD EVALUATION LM3205TL
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM3205TLEV

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 0.8 ~ 3.6V
• Current - Output: 650mA
• Voltage - Input: 2.7 ~ 5.5V
• Regulator Topology: Buck
• Frequency - Switching: 2MHz
• Board Type: Fully Populated
• Utilized Ic / Part: LM3205
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Power - Output: -

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4.
5.
BOARD LAYOUT FLOW (LLP)
1.
2.
3.
4.
Connect C1(-), C2(-) and PGND with wide GND pattern.
This pattern should be short, so C1(-), C2(-), and PGND
should be as close as possible. Then connect to a PCB
common GND pattern with as many via-holes as
possible.
SGND should not connect directly to PGND. Connecting
these pins under the device should be avoided. (If
possible, connect SGND to the common port of C1(-), C2
(-) and PGND.)
Minimize C1, PV
be as wide and short as possible. This is most important.
Minimize L1, C2, SW and PGND loop. These traces also
should be wide and short. This is the second priority.
Above layout patterns should be placed on the
component side of the PCB to minimize parasitic
inductance and resistance due to via-holes. It may be a
good idea that the SW to L1 path is routed between C2
(+) and C2(-) land patterns. If vias are used in these large
current paths, multiple via-holes should be used if
possible.
Connect C1(-), C2(-) and PGND with wide GND pattern.
This pattern should be short, so C1(-), C2(-), and PGND
should be as close as possible. Then connect to a PCB
common GND pattern with as many via-holes as
possible.
IN
, and PGND loop. These traces should
FIGURE 6. Evaluation Board for LLP
16
6.
7.
5.
6.
7.
Note: The evaluation board shown inFigure 5and Figure 6 for the
V
these pins under the device should be avoided. It is good
idea to connect V
injection to the V
FB line should be protected from noise. It is a good idea
to use an inner GND layer (if available) as a shield.
SGND should connect directly to PGND through a single
common via as close to C1 as possible. Connecting
these pins under the LLP device on a different layer
should be avoided.
V
these pins under the device should be avoided. It is good
idea to connect V
injection to the V
FB line should be protected from noise. It is a good idea
to use an inner GND layer (if available) as a shield.
LM3205TL/LM3205SD were designed with these considerations, and
it shows good performance. However some aspects have not been
optimized because of limitations due to evaluation-specific require-
ments. The board can be used as a reference, but it is not the best.
Please refer questions to a National representative.
DD
DD
should not be connected directly to PV
should not be connected directly to PV
20158032
DD
DD
DD
DD
line.
line.
to the C1(+) to avoid switching noise
to the C1(+) to avoid switching noise
IN
IN
. Connecting
. Connecting