CDB-43L21 Cirrus Logic Inc, CDB-43L21 Datasheet - Page 52

• Manufacturer Part Number: CDB-43L21
• Description: EVAL BOARD FOR CS43L21
• Manufacturer: Cirrus Logic Inc

Specifications of CDB-43L21

• Number Of Dac's: 2
• Number Of Bits: 24
• Outputs And Type: 2, Single Ended
• Sampling Rate (per Second): 96k
• Data Interface: I²C, SPI™
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Utilized Ic / Part: CS43L21
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1282; CDB-43L21

52
6.16
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
6.17
Reserved
Reserved
7
7
Limiter RELEASE Rate (RRATE[5:0])
Default: 111111
Function:
Sets the rate at which the limiter releases the digital attenuation from levels below the minimum setting in
the limiter threshold register, and returns the analog output level to the AOUTx_VOL[7:0] setting.
The limiter release rate is user selectable but is also a function of the sampling frequency, Fs, and the
DAC_SZC setting unless the disable bit is enabled.
Limiter Attack Rate Register (Address 1Bh)
Limiter Attack Rate (ARATE[5:0])
Default: 000000
Function:
Sets the rate at which the limiter attenuates the analog output from levels above the maximum setting in the
limiter threshold register.
The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and the
DAC_SZC setting unless the disable bit is enabled.
Status (Address 20h) (Read Only)
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A ”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0.
Serial Port Clock Error (SP_CLK Error)
Default: 0
Function:
Indicates an invalid MCLK to LRCK ratio. See
ing” on page 28
Note:
Binary Code
Binary Code
SP_CLKERR
000000
000000
111111
111111
On initial power up and application of clocks, this bit will be high as the serial port re-synchronizes.
Reserved
···
···
6
6
for valid clock ratios.
SPEA_OVFL
ARATE5
5
5
Slowest Release
Fastest Release
Release Time
Slowest Attack
Attack Time
Fastest Attack
···
···
SPEB_OVFL
ARATE4
4
4
“Serial Port Clocking” section on page 28“Serial Port Clock-
PCMA_OVFL PCMB_OVFL
ARATE3
3
3
ARATE2
2
2
Reserved
ARATE1
1
1
CS43L21
Reserved
ARATE0
DS723A1
0
0